WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
https://gitee.com/wangxuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial
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XDMA exhibits abnormal behavior when transfer size larger than 256 #5

Open kahuuchino opened 7 months ago

kahuuchino commented 7 months ago

I'm trying to connect XDMA IP core to DDR. When I try to transfer a 1.2 MB file(I set the size to 1268736), I find the XDMA AXI interface split the data stream with an unknown len. I have try other size, and finally I found this will happen when transfer size larger than 256. axi_interface This picture shows what will happen on AXI write channel when I set the size to 512, AXI_DWIDTH to 128. In fact, it will send 25(116+8+1)128bit data when awlen gets 18(h). I have a lot of trouble on it because my memory interface has another data width and I must finish a gearbox on it. I think this problem maybe come from XDMA linux driver or linux library functions. I have try to split my data in xdma_rw.c, but it still no work when transfer for a time(about 5KB).

One more thing, AXI interface address indicates bytes address. It means one address corresponds to 8bit data, not your AXI data width.

kahuuchino commented 7 months ago

上面是我在练习英文表达写的,下面是中文描述。 我在试着把XDMA和DDR连接起来,但当我尝试传输一个1.2MB的文件(size设置为1268736)时,我发现XDMA的AXI接口以一个未知的间隔将数据分割了。 我经过尝试发现只要size大于256就会出现这个问题。 上图展示了我将size设置为512时出现的问题,此时AXI数据宽度为128。实际上,当awlen指示18(h)时,AXI会传输25(116+8+1)128bit的数据。这给我带来了很多麻烦,因为我的DDR接口数据位宽不一样。 我感觉这个问题来源于XDMA的linux驱动或是linux库函数。 我尝试着在xdma_rw.c中分割我的数据,但传输大约5KB后终止。(分割间隔为256)

我还发现AXI接口上的地址是以字节编码的,这意味着一个地址对应着一个字节,而不是以AXI数据位宽定义的一组数据。