lars-t-hansen
commented
7 years ago Seems to me that for option 3 there are plausible optimizations that would make this practical. Suppose {i32,i64}.addc takes three inputs, op2 on the top, op1 below, carry at the bottom and produces two outputs, result on top and carry below it. For the sake of argument assume the carry is always the same type as the other operands. Define addc only to use the low bit of the carry and for the carry left after the operation to be zero or one. Things are now reasonably set up for a multi-word add, say. In a suitably unrolled loop a JIT/Wasm compiler really ought to be able to see that it is the carry that is being propagated, and generate good code. (And if the loop is not unrolled then loop overhead will dilute the carry extraction/insertion anyway.) I think worst-case branch-free code for carry extraction should be mov rd, 0; adc rd, 0; for insertion, something like and rc, 1; add rc, ~0 where rc is a register that contains a value to be treated as a carry.
On ARM, consuming a carry is separate from producing a carry: ADC consumes, ADC.S consumes and produces, ADD.S only produces. Would we want all these variants? And what about overflow?
(There might be a fourth option, where we add a operate-and-branch-on-condition operation which both produces a result and branches to a label or not, eg, i32.addc op1 op2 carry L would branch to L on carry set and fall through on carry clear, and either way leave a result on the stack, but it seems harder to use in general than the three options you suggested.)
jfbastien
ghost
mpfau
dmlloyd
dschuff
(This is an expanded version of issue (https://github.com/WebAssembly/spec/issues/446))
Multi-precision arithmetic requires special handling. This is available in some form in all ISAs, but not currently available in webasm.
There are basically three ways of doing this (it seems to me), none of which is especially palatable in the context of the current design:
Option 1. Add a special flags register, together with instructions that do arithmetic with that register.
This is the traditional approach in mainstream hardware.
You get instructions like
addc
which will add two numbers, and the value of the carry flag, and set the carry flag on the result.
This is not pleasant because it adds a special register.
Option 2. Support a form of 60bit arithmetic with 4 bits for flags.
Option 3. Support multi-word arithmetic: addition takes 3 arguments and produces 2 outputs.
This approach will do the least damage to the existing ISA and register architecture. However, this will be hard to map to existing hardware efficiently (not all hardware ISAs support loading the flags register directly.
However it is done, multi-precision arithmetic is quite important and very hard to emulate without some simple hardware support.