is `u65` a Typo?

[wucke13]

https://github.com/WebAssembly/memory64/blob/c5804d2e9a00de4860a6cbdd27bb00e16c6cc584/proposals/memory64/Overview.md?plain=1#L266

[dschuff]

Actually I think this is intentional. See for example the spec for memory32 (https://webassembly.github.io/spec/core/syntax/instructions.html#syntax-instr-memory) says that the effective address is calculated and bounds-checked as 33 bits (rather than wrapping). So this behavior is consistent with that (with the one practical difference that no real architecture actually has addresses of more than 48 bits AFAIK; so there would never be that carry in practice).

[programmerjake]

with the one practical difference that no real architecture actually has addresses of more than 48 bits AFAIK; so there would never be that carry in practice).

that's not true anymore: some recent Intel and AMD CPUs support 57-bit addressing

also RISC-V has optional support for 57-bit addressing

[dschuff]

with the one practical difference that no real architecture actually has addresses of more than 48 bits AFAIK; so there would never be that carry in practice).

that's not true anymore: some recent Intel and AMD CPUs support 57-bit addressing

also RISC-V has optional support for 57-bit addressing

Thanks, TIL. But it doesn't really change my point that the effective address calculation happens with a larger range than the address values can have, but that for the 64-bit case, real addresses (even 57-bit ones) can't overflow.

[programmerjake]

128-bit RISC-V presumably supports >64-bit memory mappings (so >2^64 bytes in size), which is the main reason for having 128-bit RISC-V https://github.com/riscv/riscv-isa-manual/blob/98918c844281332f4e75ad7d4c818ad9ecaeb5ad/src/rv128.adoc

[sbc100]

Closing as WAI

[wucke13]

Thank you all for the interesting discussion!