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WeiChungWu / vim-SystemVerilog

SystemVerilog syntax highlight/indent support in vim
MIT License
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Is it possible to enhance the indent for "UVM_INFO" like sentences? #4

Open yuhaos opened 7 years ago

yuhaos commented 7 years ago

Hi WeiChung,

Thanks for you SystemVerilog plugins, it helps me a lot in implenting verification environment. I am writing to ask for one enhancement of this plugins for uvm_info sentences.

If we start one "if" block, the third lines will deindent automically if there is ':' in the seconde line. The example is as below: image

I am very happy witht the implement now that the third line will deindent. However, if the sencond line is a uvm Macro, which has no ':', the third line will not deindent. Examples: image

I wondering is it possible to add the support for such scenarios? The scenarios could be as following also: image image

I understand that process all the Macros without ':' could be very difficult as it may need verilog syntax compiler help. However, if we limit the macros of the second line to uvm_info/uvm_error/uvm_warning/uvm_fatal, is it possible to support the de-indent automically at third line?

Thanks & Regards Yuhao

WeiChungWu commented 7 years ago

Hi Yuhao,

I am glad to know this plugin is helpful to you. Your assumption is correct. The uvm_info is treated as a open statement that means is not completed one. Therefore the indent should be kept. If you look into the indent file, you will find there are many rules to deal the exceptions. The rules are added one by one when I found an exception in the bench that may be from my colleagues. I can try to fix it as your expectation in my leisure time. (I am busy in my full-time job now.) So far, I will recommend use a begin-end pair the enclosed the "if" statement to keep indent correctly. It should be worked no matter the statement is open or not.

Thanks, WeiChung

yuhaos commented 7 years ago

Hi WeiChung,

Yes, using "begin ... end" is a nice workaround for the moment.

I am vert happy to bring this reuqirement into your view, and thank you for considering of enhancing it as one choice. I do agree that it's a slight feature and should do with low priority.

By they way, since system-verilog has no IDE, vim with the vim-SystemVerilog seems one of the best solution for the moment, we really appriciate your work with this plugin.

Thanks & Regards Yuhao