Open Wenzel opened 4 years ago
Documentation:
Also, it looks like this feature has already been implemented in kvmi-semantic
crate:
https://github.com/kylerky/kvmi-rs/blob/master/kvmi-semantic/src/memory/address_space.rs#L210
cc @kylerky can you tell us more about the state virtual address translation in kvmi-semantic
?
Currently, it supports translation for Intel CPUs operating in IA32e mode (or 64-bit mode). 32-bit mode and others are not supported. In theory, it can do translation for all of the valid mappings, i.e, 4K, 2M and 1G mappings. However, I only have a unit test for the 2M case.
By the way, it assumes that the page entry it get is valid as dictated by the Intel manual (Reserved bits are 0s and so on).
Reference: Intel Developer Manuals, Volume 3, 4.5 4-Level Paging
Another goal is to translate a virtual address to a physical address.
This implies parsing the page tables. Now either the hypervisor supports this already and can offer us an API, or we have to implement this ourselves.
Check from existing crates like x86_64 from rust-osdev if they can share page tables structures definition, and even the translation functions.