Open Willmish opened 1 year ago
From @JDuchniewicz : How is I2C handled? is it a hardware setup? code in FPGA? (probably hardware regisers etc). How can we access Wishbone and I2C
EDIT: I will be trying to build the toolkit on a pure x86-64 machine (currently doing on an emulated machine on an ARM M1 device)
Building of https://github.com/QuickLogic-Corp/qorc-sdk/tree/master/qf_apps/qf_helloworldhw seems to be broken for FPGA synthesis (install never fully succeeds for me of the envsetup (from https://github.com/QuickLogic-Corp/qorc-sdk/blob/master/envsetup.sh), neither the Docker container: https://github.com/QuickLogic-Corp/quicklogic-fpga-toolchain/tree/71302a5e4b4122976ac9c6e90597146b93083525#3-run-symbiflow-in-a-container , I tried building the yosys fork from scratch (https://github.com/antmicro/yosys/tree/quicklogic-rebased) but there are still issues like this one: https://forum.quicklogic.com/viewtopic.php?t=234
Can we deploy ML model alongside M4 app on the cortex m4, or can we somehow convert it to verilog and synthesize to be flashed on fpga?????
(If we can't deploy the model on the fpga, what else can we use it for?
@JDuchniewicz add more as needed:
We need - I2C communication working, easily portable to Zephyr. I am guessing we will need to use the Wishbone bus?
List of questions for quickLogic about EOS S3: