Currently the divider for the C08_X4 clock is hard coded (as upstream I set it to the default (6)). Instead we want to read it from its register and recalculate the value:
Next issue we have to figure out is how do we get the FFE_X1_CLK frequency when setting up I2C Clock frequency here: https://github.com/Willmish/bibop-zephyr-eos-s3/blob/5e4f189e0870c39bbbc3b1c6b89272f52964215c/app/src/eoss3_hal_i2c.c#L136 . We need this, because previously the FreeRTOS-heavy S3x_Clk_Get_Rate() was used and we don't want that. Since C08_X1_CLK is always 1/4 of C08_X4_CLK, its a Fixed Divide clock, and all we need is read the C08_X4 clock then divide it by CLK_Control_C_0 divider value (which by default is 6) and then 4. For now, I eyeballed the value to be 10000, and it works, somehow lol.
This in turn call Sx3_Clkd_Get_Hsosc_Rate(), where HSOSC is the High Speed Oscillator Clock, which can be modified but by default starts as OSC_GET_FREQ_INC macro with value: (((AIP->OSC_CTRL_1 & 0xFFF)+3)*32768).
Currently the divider for the C08_X4 clock is hard coded (as upstream I set it to the default (6)). Instead we want to read it from its register and recalculate the value:
Next issue we have to figure out is how do we get the FFE_X1_CLK frequency when setting up I2C Clock frequency here: https://github.com/Willmish/bibop-zephyr-eos-s3/blob/5e4f189e0870c39bbbc3b1c6b89272f52964215c/app/src/eoss3_hal_i2c.c#L136 . We need this, because previously the FreeRTOS-heavy
S3x_Clk_Get_Rate()was used and we don't want that. Since C08_X1_CLK is always 1/4 of C08_X4_CLK, its a Fixed Divide clock, and all we need is read the C08_X4 clock then divide it by CLK_Control_C_0 divider value (which by default is 6) and then 4. For now, I eyeballed the value to be 10000, and it works, somehow lol.Funciton being called: https://github.com/QuickLogic-Corp/qorc-sdk/blob/d61d064146c0ee927aa12b088b3bbbce60615f4d/Libraries/Power/src/s3x_clock.c#L1199 ,which in turn calls s3x_clkd_grate. This function gets the Clock source rate and divides it appropriately: by first calling s3x_clkd_get_src_rate. If the clock being called is a SRC Clock (which C08_X4 is, according to s3x_pwr_cfg_prototype line here), and C08_X1 is a Synced fix divide clock (.type = FD_CLK) , we can simply get the Source Clock frequency, divide by the set up division factor and by 4.
This in turn call Sx3_Clkd_Get_Hsosc_Rate(), where HSOSC is the High Speed Oscillator Clock, which can be modified but by default starts as
OSC_GET_FREQ_INCmacro with value:(((AIP->OSC_CTRL_1 & 0xFFF)+3)*32768).Potentially there is an error here: https://github.com/QuickLogic-Corp/qorc-sdk/blob/d61d064146c0ee927aa12b088b3bbbce60615f4d/Libraries/Power/src/s3x_clock.c#L683 . If clkd->type is FD_CLK and clock is CL08_X1, the source frequency will only be divided by 4 once, and not by the dividor of the source (i nthis case, CL08_X4).