Make circuit wiring match Verilog conventions

Witt-Phillips / reservoir-compiler

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Make circuit wiring match Verilog conventions #5

Open Witt-Phillips opened 2 months ago

Witt-Phillips commented 2 months ago

Currently inverse order for input/output circuits. My tuple structure (outputRes, x, inputRes, y) means: the x output of outputRes is wired into the y input of inputRes