Closed Haxrox closed 1 year ago
Reviewing: https://github.com/WorldofKerry/Python2Verilog/blob/6ca0a18ac1182d15249d682588c311fd96b8bfbb/docs/for_loop_limitation.md
A few questions:
Work then Loop
Loop
done
valid
is_done
From #141
Changes in #145
Reviewing: https://github.com/WorldofKerry/Python2Verilog/blob/6ca0a18ac1182d15249d682588c311fd96b8bfbb/docs/for_loop_limitation.md
A few questions:
Work then Loop
be under theLoop
state?done
,valid
signals from the callee?is_done
anddone
?