Closed WorldofKerry closed 1 year ago
Currently all variables are treated as 32-bit signed integers.
Perhaps add an optional argument for default value (is mandatory if we don't want to accidentally infer a d-flip-flop instead of a wire).
Necessary to support other types such as static-arrays.
Context of the IR should be different from the context of the verilog module (e.g. in Verilog, states and constants should be combined to localparams)
Being addressed in #73
WorldofKerry
commented
1 year ago WorldofKerry
commented
1 year ago
Currently all variables are treated as 32-bit signed integers.
Perhaps add an optional argument for default value (is mandatory if we don't want to accidentally infer a d-flip-flop instead of a wire).
Necessary to support other types such as static-arrays.
Context of the IR should be different from the context of the verilog module (e.g. in Verilog, states and constants should be combined to localparams)