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Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug
Apache License 2.0
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Unusual use of `&` in expression #15

Closed taralx closed 2 months ago

taralx commented 2 months ago

https://github.com/Wren6991/Hazard3/blame/a4412c0b00fd67788e42bc61599bf7a8c106d7b1/hdl/hazard3_core.v#L949

It strikes me that this is likely a typo. Probably harmless, but I thought I'd point it out.

Wren6991 commented 2 months ago

Thanks, this is definitely a typo, and also changes the precedence. When parsed with this precedence:

x_amo_phase == (3'h1 & bus_dph_ready_d) && !bus_dph_err_d && bus_dph_exokay_d

The effect is to also not delay IRQ entry during AMO phase 0 (read address phase) when there is a bus stall and an exclusive OK response.

I think this case is 100% unreachable when the bus fabric is well-behaved, since the core is designed to not pipeline exclusives (illegal in AHB5) and therefore there is no HEXOKAY response coincident with an AMO address phase. I'll add a property to check this, and fix up the typo. Thanks for the report.

Wren6991 commented 2 months ago

Actually this was already covered by the bus compliance checks, but I added a more direct property anyway. Seems unreachable, so no bug here, just some dubious code.

Edit: ignore my backwards comments about precedence, must have been having a slow day. Anyway, fixed, thank you.