Wren6991
commented
2 years ago Ah, yeah, I haven't been running them recently. The iCE40 one is almost certainly because example_soc.v is not disabling debug/PMP and it's going over area.
Closed gojimmypi closed 2 years ago
Wren6991
commented
2 years ago Ah, yeah, I haven't been running them recently. The iCE40 one is almost certainly because example_soc.v is not disabling debug/PMP and it's going over area.
Wren6991
commented
2 years ago Actually it seems like Yosys might be failing to trim the IRQ priority, enable, force etc flops, which is dumping 3k+ flops into the design. I'll have a look tomorrow.
At the moment development is still moving fairly fast, so you should expect things to occasionally be broken. It's almost feature complete now, so hopefully things will stabilise over the next couple of months.
gojimmypi
commented
2 years ago Of course! I hadn't considered the breaking daily release.
Any suggestion on which to use? They appear to be all daily releases, with no indication of "Stable".
Thank you for your reply.
Wren6991
commented
2 years ago There is no stable release, yet. I'm planning to go straight to a 1.0 release in a couple of months or so.
Actually it seems like Yosys might be failing to trim the IRQ priority, enable, force etc flops
Believe this is fixed by https://github.com/Wren6991/Hazard3/commit/c594ec42e97a64b72ee6cda55b281e8731c5e1af
I haven't looked at ECP5 yet
gojimmypi
commented
2 years ago Ah, I meant if you had a suggestion for stable yosys, etc.
Wren6991
commented
2 years ago Looks like ECP5 was broken by this commit
https://github.com/Wren6991/Hazard3/commit/5d6b5a80b0ede1c75564923fa627388759f5d392
Fixed by 787a7ec372d4
Wren6991
commented
2 years ago Ah, I meant if you had a suggestion for stable yosys, etc.
I tend to just use a fairly recent master build
gojimmypi
commented
2 years ago Aha, I misunderstood the root cause. I thought it was a yosys problem.
Wren6991
commented
2 years ago Yosys was not constant-trimming something I expected to be constant-trimmed, and the area blew up as a result. It's fixed by a change in the RTL style to make the constant propagation more obvious to the tools. As for whose fault it is... no idea, but it's fixed :)
Let me know if things work better for you now, I don't have nextpnr on this machine currently.
gojimmypi
commented
2 years ago your changes appear to have fixed the build for both the iCEBreaker and ULX3S! :)
curiously the ULX3S takes considerably longer to complete.
there are still some warnings:
Warning: Encountered `translate_off' comment! Such legacy hot comments are supported by Yosys, but are not part of any formal language specification. Using a portable and standards-compliant construct such as `ifdef is recommended!
Warning: Replacing memory \req_stratified with list of registers. See ../../hdl/arith/hazard3_onehot_priority_dynamic.v:37, ../../hdl/arith/hazard3_onehot_priority_dynamic.v:35
Warning: Replacing memory \fifo_valid with list of registers. See ../../hdl/hazard3_frontend.v:133
Warning: Replacing memory \fifo_valid_hw with list of registers. See ../../hdl/hazard3_frontend.v:135, ../../hdl/hazard3_frontend.v:132
Warning: Replacing memory \fifo_err with list of registers. See ../../hdl/hazard3_frontend.v:131
Warning: Replacing memory \fifo_predbranch with list of registers. See ../../hdl/hazard3_frontend.v:130
Warning: Replacing memory \fifo_mem with list of registers. See ../../hdl/hazard3_frontend.v:129
../../hdl/hazard3_pmp.v:107: Warning: Range [0:-1] select out of bounds on signal `\cfg_wdata': Setting 1 LSB bits to undef.
Warning: Replacing memory \tdata2 with list of registers. See ../../hdl/hazard3_triggers.v:86
Warning: Replacing memory \mcontrol_execute with list of registers. See ../../hdl/hazard3_triggers.v:84
Warning: Replacing memory \mcontrol_u with list of registers. See ../../hdl/hazard3_triggers.v:83
Warning: Replacing memory \mcontrol_m with list of registers. See ../../hdl/hazard3_triggers.v:82
Warning: Replacing memory \mcontrol_action with list of registers. See ../../hdl/hazard3_triggers.v:81
Warning: Replacing memory \tdata1_dmode with list of registers. See ../../hdl/hazard3_triggers.v:79
../../hdl/hazard3_triggers.v:73: Warning: Range [0:-1] select out of bounds on signal `\cfg_wdata': Setting 1 LSB bits to undef.
Warning: Replacing memory \mem with list of registers. See ../libfpga/common/sync_fifo.v:70, ../libfpga/common/sync_fifo.v:65
Warning: Replacing memory \buf_hmastlock with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:152
Warning: Replacing memory \buf_hprot with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:151
Warning: Replacing memory \buf_hburst with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:150
Warning: Replacing memory \buf_hsize with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:149
Warning: Replacing memory \buf_hwrite with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:148
Warning: Replacing memory \buf_haddr with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:147
Warning: Replacing memory \buf_htrans with list of registers. See ../libfpga/busfabric/ahbl_arbiter.v:146
Warning: Replacing memory \mem with list of registers. See ../libfpga/common/sync_fifo.v:70, ../libfpga/common/sync_fifo.v:65
Warning: Replacing memory \real_dualport_reset.mem with list of registers. See ../../hdl/hazard3_regfile_1w2r.v:40
Warning: Replacing memory \fifo_valid with list of registers. See ../../hdl/hazard3_frontend.v:133
Warning: Replacing memory \fifo_valid_hw with list of registers. See ../../hdl/hazard3_frontend.v:135, ../../hdl/hazard3_frontend.v:132
Warning: Replacing memory \fifo_err with list of registers. See ../../hdl/hazard3_frontend.v:131
Warning: Replacing memory \fifo_predbranch with list of registers. See ../../hdl/hazard3_frontend.v:130
Warning: Replacing memory \fifo_mem with list of registers. See ../../hdl/hazard3_frontend.v:129
Warning: Replacing memory \req_stratified with list of registers. See ../../hdl/arith/hazard3_onehot_priority_dynamic.v:37, ../../hdl/arith/hazard3_onehot_priority_dynamic.v:35
Warning: Replacing memory \fifo_valid with list of registers. See ../../hdl/hazard3_frontend.v:133
Warning: Replacing memory \fifo_valid_hw with list of registers. See ../../hdl/hazard3_frontend.v:135, ../../hdl/hazard3_frontend.v:132
Warning: Replacing memory \fifo_err with list of registers. See ../../hdl/hazard3_frontend.v:131
Warning: Replacing memory \fifo_predbranch with list of registers. See ../../hdl/hazard3_frontend.v:130
Warning: Replacing memory \fifo_mem with list of registers. See ../../hdl/hazard3_frontend.v:129
Warning: Replacing memory \req_stratified with list of registers. See ../../hdl/arith/hazard3_onehot_priority_dynamic.v:37, ../../hdl/arith/hazard3_onehot_priority_dynamic.v:35
Warning: Wire fpga_ulx3s.\dbg [7] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [6] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [5] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [4] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [3] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [2] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [1] is used but has no driver.
Warning: Wire fpga_ulx3s.\dbg [0] is used but has no driver.
ABC: Warning: The network is combinational.
Warnings: 32 unique messages, 46 totalOne warning is of a failure:
Warning: ABC: execution of command ""/mnt/c/download/yosyshq/oss-cad-suite/lib/yosys-abc" -s -f /tmp/yosys-abc-Yve1cs/abc.script 2>&1" failed: return code 134.
but otherwise bin files created for iCEBreaker:
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3
0 $ make -f Icebreaker.mk
>>> Synth
yosys -p "read_verilog -I../../hdl -DFPGA -DFPGA_ICE40 ../fpga/fpga_icebreaker.v ../libfpga/common/reset_sync.v ../libfpga/common/fpga_reset.v ../libfpga/common/activity_led.v ../libfpga/cdc/sync_1bit.v ../soc/example_soc.v ../../hdl/hazard3_core.v ../../hdl/hazard3_cpu_1port.v ../../hdl/hazard3_cpu_2port.v ../../hdl/arith/hazard3_alu.v ../../hdl/arith/hazard3_branchcmp.v ../../hdl/arith/hazard3_mul_fast.v ../../hdl/arith/hazard3_muldiv_seq.v ../../hdl/arith/hazard3_onehot_encode.v ../../hdl/arith/hazard3_onehot_priority.v ../../hdl/arith/hazard3_onehot_priority_dynamic.v ../../hdl/arith/hazard3_priority_encode.v ../../hdl/arith/hazard3_shift_barrel.v ../../hdl/hazard3_csr.v ../../hdl/hazard3_decode.v ../../hdl/hazard3_frontend.v ../../hdl/hazard3_instr_decompress.v ../../hdl/hazard3_pmp.v ../../hdl/hazard3_power_ctrl.v ../../hdl/hazard3_regfile_1w2r.v ../../hdl/hazard3_triggers.v ../../hdl/debug/dtm/hazard3_jtag_dtm.v ../../hdl/debug/dtm/hazard3_jtag_dtm_core.v ../../hdl/debug/cdc/hazard3_apb_async_bridge.v ../../hdl/debug/cdc/hazard3_reset_sync.v ../../hdl/debug/cdc/hazard3_sync_1bit.v ../../hdl/debug/dm/hazard3_dm.v ../libfpga/peris/uart/uart_mini.v ../libfpga/peris/uart/uart_regs.v ../libfpga/common/clkdiv_frac.v ../libfpga/common/sync_fifo.v ../libfpga/peris/spi_03h_xip/spi_03h_xip.v ../libfpga/peris/spi_03h_xip/spi_03h_xip_regs.v ../libfpga/mem/ahb_cache_readonly.v ../libfpga/mem/ahb_cache_writeback.v ../libfpga/mem/cache_mem_set_associative.v ../libfpga/mem/sram_sync.v ../libfpga/mem/ahb_sync_sram.v ../libfpga/busfabric/ahbl_crossbar.v ../libfpga/busfabric/ahbl_splitter.v ../libfpga/busfabric/ahbl_arbiter.v ../libfpga/common/onehot_mux.v ../libfpga/common/onehot_priority.v ../libfpga/busfabric/ahbl_to_apb.v ../libfpga/busfabric/apb_splitter.v; synth_ice40 -dsp; write_json fpga_icebreaker.json" > synth.log
tail -n 35 synth.log
51.53. Printing statistics.
=== fpga_icebreaker ===
Number of wires: 3217
Number of wire bits: 20276
Number of public wires: 3217
Number of public wire bits: 20276
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 5500
SB_CARRY 381
SB_DFF 3
SB_DFFE 113
SB_DFFER 895
SB_DFFES 17
SB_DFFESR 32
SB_DFFNR 1
SB_DFFR 99
SB_DFFS 8
SB_LUT4 3943
SB_RAM40_4K 4
SB_SPRAM256KA 4
51.54. Executing CHECK pass (checking for obvious problems).
Checking module fpga_icebreaker...
Found and reported 0 problems.
52. Executing JSON backend.
Warnings: 23 unique messages, 37 total
End of script. Logfile hash: f84a88a709, CPU: user 55.14s system 0.52s, MEM: 317.92 MB peak
Yosys 0.20+70 (git sha1 6e907acf8, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 49% 11x proc_mux (29 sec), 10% 55x opt_expr (6 sec), ...
>>> Place and Route
nextpnr-ice40 -r --up5k --package sg48 --pcf fpga_icebreaker.pcf --json fpga_icebreaker.json --asc fpga_icebreaker.asc --timing-allow-fail --quiet --log pnr.log
Info: Max frequency for clock 'tck$SB_IO_IN_$glb_clk': 42.64 MHz (PASS at 12.00 MHz)
>>> Generate Bitstream
icepack -s fpga_icebreaker.asc fpga_icebreaker.bin
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3and bin files also successfully created for ULX3S:
0 $ make clean
rm -f fpga_icebreaker.json fpga_icebreaker.asc fpga_icebreaker.bin fpga_icebreaker_synth.v
rm -f synth.log pnr.log
rm -f pnr_try*.asc pnr*.log
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3
0 $ make -f ULX3S.mk
>>> Synth
yosys -p "read_verilog -I../../hdl -DFPGA -DFPGA_ECP5 ../fpga/fpga_ulx3s.v ../fpga/pll_25_50.v ../fpga/pll_25_40.v ../libfpga/common/reset_sync.v ../libfpga/common/fpga_reset.v ../soc/example_soc.v ../../hdl/hazard3_core.v ../../hdl/hazard3_cpu_1port.v ../../hdl/hazard3_cpu_2port.v ../../hdl/arith/hazard3_alu.v ../../hdl/arith/hazard3_branchcmp.v ../../hdl/arith/hazard3_mul_fast.v ../../hdl/arith/hazard3_muldiv_seq.v ../../hdl/arith/hazard3_onehot_encode.v ../../hdl/arith/hazard3_onehot_priority.v ../../hdl/arith/hazard3_onehot_priority_dynamic.v ../../hdl/arith/hazard3_priority_encode.v ../../hdl/arith/hazard3_shift_barrel.v ../../hdl/hazard3_csr.v ../../hdl/hazard3_decode.v ../../hdl/hazard3_frontend.v ../../hdl/hazard3_instr_decompress.v ../../hdl/hazard3_pmp.v ../../hdl/hazard3_power_ctrl.v ../../hdl/hazard3_regfile_1w2r.v ../../hdl/hazard3_triggers.v ../../hdl/debug/dtm/hazard3_jtag_dtm.v ../../hdl/debug/dtm/hazard3_jtag_dtm_core.v ../../hdl/debug/cdc/hazard3_apb_async_bridge.v ../../hdl/debug/cdc/hazard3_reset_sync.v ../../hdl/debug/cdc/hazard3_sync_1bit.v ../../hdl/debug/dm/hazard3_dm.v ../libfpga/peris/uart/uart_mini.v ../libfpga/peris/uart/uart_regs.v ../libfpga/common/clkdiv_frac.v ../libfpga/common/sync_fifo.v ../libfpga/cdc/sync_1bit.v ../libfpga/peris/spi_03h_xip/spi_03h_xip.v ../libfpga/peris/spi_03h_xip/spi_03h_xip_regs.v ../libfpga/mem/ahb_cache_readonly.v ../libfpga/mem/ahb_cache_writeback.v ../libfpga/mem/cache_mem_set_associative.v ../libfpga/mem/sram_sync.v ../libfpga/mem/ahb_sync_sram.v ../libfpga/busfabric/ahbl_crossbar.v ../libfpga/busfabric/ahbl_splitter.v ../libfpga/busfabric/ahbl_arbiter.v ../libfpga/common/onehot_mux.v ../libfpga/common/onehot_priority.v ../libfpga/busfabric/ahbl_to_apb.v ../libfpga/busfabric/apb_splitter.v ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v; hierarchy -top fpga_ulx3s; synth_ecp5 -abc9 -json fpga_ulx3s.json" > synth.log
tail -n 35 synth.log
Removed 0 unused modules.
54.47. Printing statistics.
=== fpga_ulx3s ===
Number of wires: 7860
Number of wire bits: 27851
Number of public wires: 7860
Number of public wire bits: 27851
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 9708
CCU2C 210
DP16KD 64
EHXPLLL 1
JTAGG 1
L6MUX21 633
LUT4 5808
MULT18X18D 3
PFUMX 1572
TRELLIS_DPR16X4 32
TRELLIS_FF 1384
54.48. Executing CHECK pass (checking for obvious problems).
Checking module fpga_ulx3s...
Found and reported 0 problems.
54.49. Executing JSON backend.
Warnings: 32 unique messages, 46 total
End of script. Logfile hash: 46793328ad, CPU: user 65.00s system 0.45s, MEM: 416.25 MB peak
Yosys 0.20+70 (git sha1 6e907acf8, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 44% 32x proc_mux (32 sec), 10% 1x abc9_exe (7 sec), ...
>>> Place and Route
nextpnr-ecp5 -r --placer sa --um5g-85k --package CABGA381 --lpf fpga_ulx3s.lpf --json fpga_ulx3s.json --textcfg fpga_ulx3s.config --timing-allow-fail --quiet --log pnr.log
Info: Max frequency for clock '$glbnet$soc_u.genblk1.genblk1.dtm_u.jtck_posedge_dont_use': 161.50 MHz (PASS at 12.00 MHz)
>>> Generate Bitstream
ecppack --compress --svf fpga_ulx3s.svf --idcode 0x41113043 fpga_ulx3s.config fpga_ulx3s.bit
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3
0 $there are still some warnings
The range warnings are due to the triggers and PMP being elaborated with a trigger and PMP region count of 0, even though they are subsequently stubbed out. This is known, and is 100% a tool issue, but I have removed the warning by adding further generate blocks inside the trigger/PMP blocks.
The debug warning is just the LEDs not being tied off in the ULX3S top level. I fixed that.
The others are useless noise. The "replacing memory with list of registers" just means that a non-packed array in your code was not inferred as a memory instance, which is not particularly useful as only the minority of non-packed arrays are actually used as memories.
gojimmypi
commented
2 years ago Excellent. Thanks very much for your prompt response and help.
Errors for Icebreaker
Following the instructions for Building an example SOC for the iCEBreaker, I ran into this error:
In more detail:
another attempt:
Errors for ULX3S
The ULX3S also has an error:
I can confirm synth_ecp5.mk:44 matches what I have locally
$(YOSYS) -p "$(SYNTH_CMD)" > synth.log:I have the latest toolchain installed, as of today, from:
Specifically there versions:
If it helps, I have a blog with more details.
Any tips on what I might be doing wrong? Thanks.