Help with JTAG DTM

[tannewt]

I'm working on a bare bones JTAG in Python and using the Hazard3 as a test bench. (Once I get the TB going then I want to get an ECP5 going.) My JTAG code is here: https://github.com/tannewt/jtag To connect to the test bench do: python connect_to_remote.py 8298 with the tb run with ./tb --port 8298.

I'm trying to read a register via DMI and getting a 0x3 error back. I may just need to add more idle cycles. I've tried the 4 as the DTMCS register says and also 6. From our Twitter conversation it sounds like I should retry with more idle cycles. Is that right?

Here is a VCD: h3_jtag.zip

[Wren6991]

Here are some relevant signals from that VCD:

• tck: JTAG test clock
• read_dmi and write_dmi: accesses to the dmi JTAG DR in the TCK domain
• dmi_busy: a DMI access is in progress downstream so a new one can not be started
• dmi_cmderr: the "busy" error you are seeing
• src_req/dst_req/src_ack/dst_ack: the 4-phase handshake used to cross bus transfers from the TCK to the core domain.
• dmi_*: actual DMI bus in core domain

So as you can see you are getting a "busy" error because the next dmi register access takes place before the downstream access has safely completed.

The 4 idle cycles are just a hint to the debugger that some idle cycles are needed. In this case it looks like you need 8, though the correct number will vary depending on the ratio of TCK to core clock. Usual practice is for the debugger to just insert one more idle cycle every time it sees the busy. Also note that the busy does not mean the transfer is lost -- you can keep clearing the error and polling for the transfer to complete, if you prefer.

The number of hint cycles is a parameter in the testbench, so I'll increase it to 8 which is apparently the right number for a 1:2 TCK:clk_dmi ratio.

[Wren6991]

I'm sure the handshake could be tightened up by a few cycles -- it's written to be quite conservative and just work.

[tannewt]

Thanks! I've added the retry on my side too.