X16Community / vera-module

Versatile Embedded Retro Adapter
MIT License
14 stars 5 forks source link

Add an ability to replay and loop FIFO data #11

Closed akumanatt closed 1 year ago

akumanatt commented 1 year ago

This update adds 2 write bits to VERA registers: AUDIO_CTRL bit 6 and AUDIO_RATE bit 7.

Writing 1 to AUDIO_CTRL bit 6 will only reset FIFO's read position to 0. This allows a sample data in the buffer to be replayed any time without refilling it again. AUDIO_RATE bit 7 set will enable looped playback where the read position is automatically reset to 0 if the buffer becomes empty in the next sample. Although an AUDIO_RATE value of 128 will still play at the maximum rate without looping.

Note that a position of 0 here means an internal buffer's address. Which means a FIFO reset (write 1 to AUDIO_CTRL bit 7) is required in order to reset the write position to 0 too before uploading a sample data and make these methods above play correctly.

visual-trials commented 1 year ago

I have tried to include these changes into the fx-branch. After doing so I found out a few things:

It is probably prudent to re-think how the logic should work and how the interface should work for this feature. Then implement that. Then LUT-optimization (and review) can be performed.

JeffreyH

akumanatt commented 1 year ago

I updated the loop method to be a combination of AUDIO_CTRL bits 6-7 now. Also, I made it reset only in IDLE state.

mooinglemur commented 1 year ago

I accidentally merged this one. If we need to revert, we can merge #19

mooinglemur commented 1 year ago

This merge has been reverted after discussions on Discord. JeffreyH has some concerns about potential timing problems in this implementation that might unfortunately be costly in LUTs to fix, and it blocks the potential merge of fx into main. Please rework this feature against the fx branch and open a new PR.