Noise PSG waveform should be AND'd with the inverted Width value

[LTVA1]

This may not be as useful as tri/saw XOR but it yields kinda interesting sound nonetheless.

I don't know if it will reduce or increase LUT usage because I have zero experience with FPGA programming and Verilog, so I haven't run any tests. However, I have modified a line in C emulator to show how it would sound, and ran some tests in Furnace.

https://github.com/X16Community/vera-module/assets/87536432/47fdb1b2-6d27-4ab3-a9de-9ac535029331

[m00dawg]

Yeah that's interesting!

I needed to port over the results from the recent #sound convo for bug #28 but to solve for the concern with compatibility, using DCSEL like FX Update does may be what needs to happen to alleviate the concerns about breaking existing songs. Basically DCSEL=7 would be used to enable audio feature flags. So something like this:

; Switch to PSG Options (DCSEL 7)
LDA VERA_CTRL
ORA #%00001110
STA VERA_CTRL

; Enable XOR
LDA PSG_OPTIONS ; ($9F29, aka DC_VIDEO when DCSEL=0)
ORA #%00000001
STA PSG_OPTIONS 

; Switch back to normal VERA registers (DCSEL 0)
LDA VERA_CTRL
AND #%11110001
STA VERA_CTRL

In the above I just set bit 0, but could have bits for each of these features (tri, saw, and noise) or just lump them together. Compatible software that wants to expose the new features can simply set the above as part of the VERA setup routine and be on their merry way. The default would be the existing behavior to avoid breaking existing songs.

I don't think this need be required as the use of the current PWM register in undocumented ways should be expected to cause issues but similarly if this can avoid breaking existing songs at all and is under the LUT budget, it would make the new sound additions much easier to add in as a result. No idea the LUT cost though.

[LTVA1]

Yeah, this would do the trick, I think. I don't know about LUT usage either so I let others decide.