As the original NMOS 6502 didn't have (zp) addressing, it used (zp),y addressing with a constant .Y = 0 for ZP indirect loads. Not only is this not necessary anymore, as both our target CPUs support (zp) addressing, it leads to behavior differences when POKE is used on addresses in the IO page: In the extra CPU cycle needed to calculate the target address during sta (zp),y, the 65C816 performs a read of an invalid address, while the 65C02 performs a read of what is presumed to be the last fetched instruction byte, causing an extra read from the IO page on the 65C816.
This PR replaces all unnecessary (zp),y usages in code17.s, where the implementation for PEEK and POKE lives.
As the original NMOS 6502 didn't have
(zp)addressing, it used(zp),yaddressing with a constant .Y = 0 for ZP indirect loads. Not only is this not necessary anymore, as both our target CPUs support(zp)addressing, it leads to behavior differences whenPOKEis used on addresses in the IO page: In the extra CPU cycle needed to calculate the target address duringsta (zp),y, the 65C816 performs a read of an invalid address, while the 65C02 performs a read of what is presumed to be the last fetched instruction byte, causing an extra read from the IO page on the 65C816.This PR replaces all unnecessary
(zp),yusages in code17.s, where the implementation forPEEKandPOKElives.