timing features don't work

[Devil-SX]

use Verilator backend, timing argument

picker export ... -sim verilator -V --timing

I use some delay assignments in my RTL code. such as a <= #(10) b

Didn't see any delay on waveform. Verilator version 5.024 supports timing features.

[Makiras]

Maybe we can check if the --timing argument has been successfully enabled for design at first? the building logs may show the status.

[Devil-SX]

Thanks for you quick reply. I think argument has been successfully enabled because without argument compile process would fail and with argument it can be compiled successfully.

[Makiras]

that's an unusual behavior, may I have your minimal code for reproduce?

[Devil-SX]

This is a minimal example for reproducing. delay.zip

If you run the current version or delete the timescale ... of Delay.v, you can't see any delay on the waveform. If you change 1ps/1ps to 1ns/1ps, you can't see any change of output signal.

What is the default period of InitClock ? I also tried add --timescale argument to verilator, but I didn't find correct form.

[Makiras]

The default period for Verilator is 1ps/1ps. Each Step() will push the clock for 1ps by default (the last one, 1ns/1ps will be 1ps). So if 1ns/1ps is changed, #10 will delay 10ns, which is 10000 ps and needs 10000 Step().

I will try to reproduce in the next few days, thanks for you artifacts.

[Makiras]

I'm sorry, but I couldn't reproduce this situation in my environment. It would be appreciated if you could provide more details about your environment.
such as verilator, python, picker, gcc, linux, environment variable version