Some code is not standard-compliant Verilog

[Icenowy]

https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/iu/rtl/multiplier_65x65_3_stage.v#L172 Here in the instance, the parameter part should have () at both sides of the number, like the code above.

Without these (), yosys will throw an error for the code, and the Verilog standard requires #() to be a part of parameter_value_assignment .

[purplelegant]

Thank you for your kind reminder! The coding style is fixed in commit 4047f29873a28a653ccbd17e584ba224feee0a55.