The XTheadFMemIdx instruction that perform a zero-extension of the index register (those with a u in the name) are identical to the sign-extension counterparts on RV32. Therefore, it does not make sense to offer both for RV32.
Further, the table lists the 8-byte loads/stores as compatible with the F extensions. However, 8-byte loads won't fit into single-precision floating-point register. And 8-byte stores can't be performed from a single-precision floating-point register. Instead of defining truncation and extension for these cases, let's make the instructions only available for those cases where they make sense.
The XTheadFMemIdx instruction that perform a zero-extension of the index register (those with a
uin the name) are identical to the sign-extension counterparts on RV32. Therefore, it does not make sense to offer both for RV32.Further, the table lists the 8-byte loads/stores as compatible with the
Fextensions. However, 8-byte loads won't fit into single-precision floating-point register. And 8-byte stores can't be performed from a single-precision floating-point register. Instead of defining truncation and extension for these cases, let's make the instructions only available for those cases where they make sense.Fixes #49.