I have a Allwinner Nezha which contains a T-Head c906 core. Attempting to read th.vlenb from S-mode raises an illegal instruction exception. The spec says:
The XTheadVector extension adds 32 vector registers, and six unprivileged CSRs (th.vstart, th.vxsat, th.vxrm, th.vl, th.vtype and th.vlenb) , which also overlap with those of the V extension (vstart, vxsat, vxrm, vl, vtype and vlenb)
I tested this on a toolchain that does not support xtheadvector, but the patch in binutils simply sets an alias of th.vlenb to the standard vlenb [1] so I used the same encoding of vlenb,
My c906 has not had any issues executing any other other supported xtheadvector operations. Is th.vlenb supposed to be supported on the c906 chips?
There is some discussion on lkml [2]. I have a patch to support xtheadvector in Linux, but because of this issue with vlenb I have opted to put the vlenb in the device tree.
I have a Allwinner Nezha which contains a T-Head c906 core. Attempting to read th.vlenb from S-mode raises an illegal instruction exception. The spec says:
I tested this on a toolchain that does not support xtheadvector, but the patch in binutils simply sets an alias of th.vlenb to the standard vlenb [1] so I used the same encoding of vlenb,
My c906 has not had any issues executing any other other supported xtheadvector operations. Is th.vlenb supposed to be supported on the c906 chips?
There is some discussion on lkml [2]. I have a patch to support xtheadvector in Linux, but because of this issue with vlenb I have opted to put the vlenb in the device tree.
[1] https://github.com/bminor/binutils-gdb/blob/3e61a22ce7bce793db9bc52ef2c30fd9070a1dd8/include/opcode/riscv-opc.h#L4557 [2] https://lore.kernel.org/linux-riscv/20240516-sleek-wound-f835b3bf23cf@spud/T/#mfc016f748de703b1f0ea9f79d1c368740cf6e0dd