request for spec of hardware side

[ray-mahong]

Hi wujian100 owners, thanks for your contribution to open the source code of wujian. But I met some trouble when I want to know more about its architecture or details inside. Could you release some document like instruction set(ISA) and illustration of module level inside it ? It looks like a user guide for software engineers more than for hardware engineers in the folder of doc.

[springluo]

when i saw the user guide ,I had the same feeling like you. The guide focuses on the software more than the hardware. And I wrote the #43 issues 10 days ago. nobody have replied me. This project seems to be unmaintained.

[ray-mahong]

That's too bad. You know I'm interested the RISC-v and willing to study some in practice. If you know more project like it, please contact me.

[hyf6661669]

@ray-mahong If you want to study how to design risc-v core, I advice you to have a look at

ariane
rocket-chip
scr1
picorv32
darkriscv
and so on...

It seems that this repo fouces on how to design/use a SoC platform, so the core itself is not the key part.

[ray-mahong]

thanks for your responses, I agree with you. I'm willing to study the list you gave.

[OpenEDF]

@ray-mahong  list is below：
1.[picorv32](https://github.com/YosysHQ/picorv32)
2.[Cores-SweRVolf](https://github.com/chipsalliance/Cores-SweRVolf)
3.[RISC-V](https://cnrv.io/resource)
4.[xiangshan](https://github.com/OpenXiangShan/XiangShan)
5.[riscv-mini](https://github.com/ucb-bar/riscv-mini)
6.[Reindeer](https://github.com/PulseRain/Reindeer)
7.[riscv-software-list](https://github.com/riscvarchive/riscv-software-list)
8.[VexRiscv](https://github.com/SpinalHDL/VexRiscv#description)
9.[RISCV-FPGA](https://github.com/Obijuan/RISC-V-FPGA)
10.[serv](https://github.com/olofk/serv)
11.[lowriscv-chip](https://github.com/lowRISC/lowrisc-chip/tree/refresh-v0.6/src)
12.[VexRiscv](https://github.com/SpinalHDL/VexRiscv)
13.[biriscv](https://github.com/ultraembedded/biriscv)
14.[Ibex](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) [github Core](https://github.com/lowRISC/ibex)
15.[simple-riscv-cpu](https://github.com/damdoy/simple_riscv_cpu)
16.[darkriscv](https://github.com/darklife/darkriscv)
17.[neorv32](https://github.com/stnolting/neorv32)
18.[linux-on-litex-vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv)
19.[kianRiscv](https://github.com/splinedrive/kianRiscV)
20.[verilator RISC-V](https://github.com/ultraembedded/riscv)
21.[RISC-V Chisel Open Source](https://awesomeopensource.com/projects/chisel/risc-v)
22.[SpinalHDL -chisel](https://github.com/SpinalHDL/SpinalHDL)
23.[rocke-chip](https://github.com/chipsalliance/rocket-chip)
24.[USTC-RVSoc](https://github.com/WangXuan95/USTC-RVSoC)
25.[FPGA RISC-V Core](https://github.com/spider-tronix/VLSI) 
26.[riscv-boom](https://github.com/riscv-boom/riscv-boom) https://boom-core.org/
27.[sifive](https://github.com/sifive)
28.[Tape-Out with U18 Technongy](https://github.com/jasonlin316/RISC-V-CPU)
29.[Open Source Libs](https://opensourcelibs.com/libs/risc-v)
30.[spu32](https://github.com/maikmerten/spu32)
31.[RISCVX](https://github.com/L1ttleFlyyy/RISCVX/tree/master/sources_1)
32.[potato](https://github.com/skordal/potato)
33.[mips-cpu](https://github.com/jmahler/mips-cpu)
34.[MIPSProcessor](https://github.com/yasnakateb/MIPSProcessor)
35.[mips-cpu-and-microsystem](https://github.com/wzp21142/mips-cpu-and-microsystem)
36.[CVA6](https://github.com/openhwgroup/cva6)
37.[e200](https://github.com/SI-RISCV/e200_opensource) [e203](https://github.com/riscv-mcu/e203_hbirdv2)
38.[Various HDL Verilog IP Cores](https://github.com/ultraembedded/cores)
39.[tinyriscv](https://github.com/liangkangnan/tinyriscv)