Closed jrwagz closed 1 year ago
Hello,
Thank you for the report. Verilator has recently started actually supporting timing delays like this and now requires this new option. I believe I fixed some other repos, but missed this one (I tend to update oss-cad-suite about once a month).
I've been curious about using Verilator as a linter, so this example has been pretty interesting. Thanks for sharing!
Yes, Verilator is awesome as lint and simulator (and makes SystemVerilog/Verilog much "safer" to use IMHO). Okay, I believe I have fixed up this repo (and the other UPduino ones) and also a few minor makefile improvements. Thanks again for the report, and if you spot anything else let me know (or hit me up with any questions on tinyVision.ai Discord).
First of all, thanks for putting together this great example for UPDuino projects, I appreciate the effort you've put in to share it!
I've clone the project and was stepping through the README and got the tools setup properly (or so at least I assume at this point). And then I attempted a build via
make bin
, and the verilator lint fails by default with the following error:Is this intended, or did something change in newer versions of the OSS Cad Suite that is causing this?
I'm using this build: https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2022-11-24
Perhaps you were assuming an older version of these tools?