Closed bo3z closed 1 year ago
Thanks @bo3z - Is there a corresponding test which needs to be updated as a result of this change to the HLS?
Thanks @bo3z - Is there a corresponding test which needs to be updated as a result of this change to the HLS?
No, in VADD, the words are streamed, so as long as they are read/written in the same manner, there will be no bugs. Problems only occur with arithmetic.
In general, however, I think it might be worth adding a few more examples/tests for PL-PL communication, maybe similar to the FPGA'23 tutorial or the above-mentioned REDUCE-SUM.
In the HLS example, word slicing is done like LSB...MSB, when, the correct way would be MSB...LSB. This will not cause any compile-time issues, but, can sometimes cause incorrect behaviour (e.g. summing words). An example of this is shown in this branch with REDUCE-SUM.
Proposing this PR for any users using the HLS test example as a baseline for their applications, as it is quite a niche bug once in the code.