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Xilinx / HLS

Vitis HLS LLVM source code and examples
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Taking .bc files in Compilation Flow #3

Open fyquah opened 3 years ago

fyquah commented 3 years ago

I am thinking of working on a tool that generate a custom HLS front-end which generates HLS-friendly LLVM-bitcode, and leverage plugins + vitis_hls backend for optimization passes and RTL generation.

How can I pass the generated bit files into the HLS compilation flow?

keryell commented 3 years ago

We have an example using another front-end in https://github.com/triSYCL/sycl, look at the sycl/unified/next branch and how v++ is fed from the Clang driver with some LLVM bitcode. Unfortunately it is not a small sample code...

keryell commented 3 years ago

There is some doc in https://github.com/triSYCL/sycl/blob/sycl/unified%2Fnext/sycl/doc/Xilinx_sycl_compiler_architecture.rst At least you can see how v++ is used with this script https://github.com/triSYCL/sycl/blob/sycl/unified/next/sycl/tools/sycl-xocc/bin/sycl-xocc This script shows for example how we use the xoccIRDowngrader to feed v++ with some LLVM IR generated by the latest LLVM. This pass is in https://github.com/triSYCL/sycl/blob/sycl/unified/next/llvm/lib/SYCL/XOCCIRDowngrader.cpp If you improve this process, keep the triSYCL team posted so we can benefit from your experience! :-)

yu810226 commented 3 years ago

If your generated LLVM IR is in 7.0 format, you can leverage the plugin with ::LLVM_CUSTOM_INPUT to pick up the your generated one and then utilizing the ::LLVM_CUSTOM_OUTPUT to pass it downwards to the flow. Else you will need to have an IR transformer for translating different version LLVM IR to the LLVM 7.0 IR, and call it before the plugin or add it into the plugin. Above triSYCL xoccIRDowngrader is another way to go for feeding v++ higher version of LLVM IR.

RicDen commented 3 years ago

@yu810226 Could you point me please to an example on how to pass LLVM 7.0 IR downwards in the flow. Also do I still need to load C++/v++ or similar into my tcl script? Thank you very much!

keryell commented 2 years ago

Our scripts and passes have been renamed to match the new Vitis/v++ tool names:

rgioiosa78 commented 2 years ago

@yu810226 I'm trying to do something similar too and I was wondering if you could provide an example of how to pass LLVM 7.0 downwards the flow? maybe a simple .tcl script? Thank you very much!

Ralender commented 2 years ago

If the LLVM you have is compatible in version with HLS's LLVM IR, you don't need to go through sycl_vxx.py(maybe you even cant) what you can simply do assuming you ir is in kernel.ll is:

.xpirbc is the "magic" extension sycl_vxx.py uses under the hood to feed LLVM IR to v++

all the other stuff sycl_vxx.py does is about downgrading IR, lowering sycl annotation into HLS annotations and removing code pattern HLS has a hard time with.

yu810226 commented 2 years ago

Hello @rgioiosa78 , The LLVM_CUSTOM_INPUT could be set to be your input.bc. And you would need the dummy source file for an empty kernel that's with the function signature met the one you your input.bc.

The tcl file would be similar to below with above mentioned change. https://github.com/Xilinx/HLS/blob/main/vitis_hls_examples/override_opt_flow_demo/run_hls.tcl

gabrielrodcanal commented 1 year ago

Hello @rgioiosa78 , The LLVM_CUSTOM_INPUT could be set to be your input.bc. And you would need the dummy source file for an empty kernel that's with the function signature met the one you your input.bc.

The tcl file would be similar to below with above mentioned change. https://github.com/Xilinx/HLS/blob/main/vitis_hls_examples/override_opt_flow_demo/run_hls.tcl

@yu810226 I tried this method but Vitis HLS complains that the top function is not found.