`ap_hs` doesn't work with `hls::stream`

[syed-ahmed]

Per this document, ap_hs is supported with hls::stream, however we fail to get ack and vld signals on the input and output ports and end up with the following warning:

WARNING: [HLS 207-5530] Unsupported interface port data type in '#pragma HLS interface ap_hs'

Is this expected? ap_hs on hls::streams worked before vitis.

Should there be ap_hs in the StreamMode bool here: https://github.com/Xilinx/HLS/blob/da538325ea9cb410672be6bb15d6c2e6220bfeb3/llvm/clang/lib/Parse/ParseXlxPragma.cpp#L2018-L2023

Here's some HLS to reproduce the issue:

#include "hls_stream.h"
#include "ap_int.h"

void user_fifo(
          hls::stream<ap_uint<32> > & Input_1,
          hls::stream<ap_uint<32> > & Output_1
        )
{
#pragma HLS INTERFACE ap_hs port=Input_1
#pragma HLS INTERFACE ap_hs port=Output_1
        int i;
        int tmp[2048];
        for (i=0; i<2048; i++)
        {
            tmp[i] = Input_1.read();
        }
        for (i=0; i<2048; i++)
        {
            Output_1.write(tmp[i]);
        }
}

[doonny]

I am having the same issue with ap_fifo. Moreover, non-blocking write and read of hls:stream interfaces can not be compiled. However, according the document (), it should be OK to use. https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/devhostapp.html

How could I modify the front-end compiler to enable non-blocking write and read of hls:stream (axis) interfaces ?

[dhananjays]

I'm having the same issue. Were you able to get a workaround for this @syed-ahmed? Thanks in advance.

[syed-ahmed]

Hi @dhananjays, I don't have a workaround for getting the exact signals that ap_hs used to infer. We ended up changing our interfaces to axis. So that would mean you will need to use TVALID/TREADY instead of vld/ack signals.