Ability to add external AXI ports to block design for use with existing RTL

Xilinx / PYNQ-Metadata

PYNQ-Metadata provides an abstract description of reconfigurable system designs.

BSD 3-Clause "New" or "Revised" License

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Ability to add external AXI ports to block design for use with existing RTL #13

Open JonathanKnoblauch opened 10 months ago

JonathanKnoblauch commented 10 months ago

I think a valuable feature in a future PYNQ release would be the ability to add external ports - in particular AXI ports to the block design for use with existing RTL without needing to re-implement the RTL in the block design itself.