Open TRnhld opened 9 months ago
btw: there is also some inconsistency of the version:
version.txt != pynqmetadata.__version__
Thanks for this. Is there any chance you could share a minimal hwh file that I can take a look at?
design4.zip It's not the minimal desing you asked for, but this is the one I debugged with. The component with the mentioned issue can be found under "/qspi_master_hier/axi_quad_spi_perf" (L 7278f)
Maybe a good option for a fix coud be:
elif addrblock.get("INTERFACE") == "aximm" and "AXI_FULL" in core.ports:
_port_available = True
_portname = "AXI_FULL"
I have tested your suggested fix here: https://github.com/STFleming/PYNQ-Metadata/tree/axi_full_register_fix
It seems to work well:
It also passes all current tests.
Would you like to submit a PR to get credit for the fix? I'm happy to do a PR from my branch if you'd prefer :)
Im fine with you doing the PR. - Thanks
In hwh_frontend.py(line 485ff) there is a check, tries to map the "INTERFACE" to a portname. If there is a AXI_Full port, the
INTERFACE
property will be "aximm" which does not match toAXI_FULL
! therefore the variable_port_available
will not be set toTrue
.part of hwh-File:
check in python