Xilinx / PYNQ

Python Productivity for ZYNQ
http://www.pynq.io/
BSD 3-Clause "New" or "Revised" License
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SPI-Core crashes python kernel / linux kernel when access register_map #1435

Closed TRnhld closed 4 months ago

TRnhld commented 9 months ago

based on this I created some sample code to see where the python kernel crashes:

from pynq import Overlay
o = Overlay(r'overlay/design7.xsa')
rs = pynq.registers.RegisterMap.create_subclass(o.qspi_master_hier.axi_quad_spi._register_name, o.qspi_master_hier.axi_quad_spi._registers)(o.qspi_master_hier.axi_quad_spi.mmio.array)
buf = o.qspi_master_hier.axi_quad_spi.mmio.array

array32 = buf.view(dtype='u4')

array32[0x10] = 0xa # resetting spi core

for k, v in rs._register_classes.items():
    index = v[1] // 4
    print("%02X "  % (v[1]//4), end='')

sleep(1)
print("\n")

for k, v in rs._register_classes.items():
    index = v[1] // 4
    if index == 0x1B:
        continue
    print("%02X "  % (v[1]//4), end='')
    sleep(0.1)
    array = array32[index:index+1]
    print("= %02X" % array[0])

sleep(1)
print("\n")

for k, v in rs._register_classes.items():
    index = v[1] // 4
    print("%02X "  % (v[1]//4), end='')
    sleep(0.1)
    array = array32[index:index+1] # axi bus gets timeout when trying to excess empty rx fifo
    print("= %02X" % array[0])

Output:

18 19 10 18 19 1C 1D 1E 07 1A 1B 08 0A 

18 = 180
19 = AD
10 = 00
18 = 180
19 = AD
1C = 01
1D = 00
1E = 00
07 = 00
1A = 00
08 = 400
0A = 00

18 = 180
19 = AD
10 = 00
18 = 180
19 = AD
1C = 01
1D = 00
1E = 00
07 # *Python kernel Restarts here*
schelleg commented 4 months ago

This is a special case when accessing the entire register map - PYNQ doesn't support this register behavior.

If this is still an issue re-open it as a discuss.pynq.io post.