PYNQ-Z2 Compiler with Vivado GUI

[Kgfu]

Sorry to one question. Built the vivado project for PYNQ-Z2 board by below command successfully:

cd PYNQ_Composable_Pipeline/boards/Pynq-Z2 make project When I trying change the static ip : ex: colorthresholding_accel to other ip I created, and compiler the project by the Vivado GUI (Generation Bitstream). I got below error message about the PREQ_HZ doesn't match between xxx and yyy:

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_0/rp_axi_lite0(142857132) and /axi_interconnect_0/m22_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_0/rp_axi_lite1(142857132) and /axi_interconnect_0/m23_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_1/rp_axi_lite0(142857132) and /axi_interconnect_0/m24_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_1/rp_axi_lite1(142857132) and /axi_interconnect_0/m25_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_fork/rp_axi_lite(142857132) and /axi_interconnect_0/m26_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_join/rp_axi_lite(142857132) and /axi_interconnect_0/m27_couplers/auto_cc/M_AXI(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_0_out0/S_AXIS(1.42857e+08) and /composable/pr_0/stream_out0(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_0_out1/S_AXIS(1.42857e+08) and /composable/pr_0/stream_out1(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_1_out0/S_AXIS(1.42857e+08) and /composable/pr_1/stream_out0(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_1_out1/S_AXIS(1.42857e+08) and /composable/pr_1/stream_out1(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_join_out0/S_AXIS(1.42857e+08) and /composable/pr_join/stream_out(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_fork_out0/S_AXIS(1.42857e+08) and /composable/pr_fork/stream_out0(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_fork_out1/S_AXIS(1.42857e+08) and /composable/pr_fork/stream_out1(142857132)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_0/stream_in0(142857132) and /composable/dfx_decouplers/pr_0_in0/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_0/stream_in1(142857132) and /composable/dfx_decouplers/pr_0_in1/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_1/stream_in0(142857132) and /composable/dfx_decouplers/pr_1_in0/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_1/stream_in1(142857132) and /composable/dfx_decouplers/pr_1_in1/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_fork/stream_in0(142857132) and /composable/dfx_decouplers/pr_fork_in0/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_join/stream_in0(142857132) and /composable/dfx_decouplers/pr_join_in0/M_AXIS(1.42857e+08)

[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_join/stream_in1(142857132) and /composable/dfx_decouplers/pr_join_in1/M_AXIS(1.42857e+08)

[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_0/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)

[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_1/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)

[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_join/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)

[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_fork/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)

[BD 41-1031] Hdl Generation failed for the IP Integrator design /home/willychiang/Desktop/PYNQ_Composable_Pipeline/boards/Pynq-Z2/cv_dfx_4_pr/cv_dfx_4_pr.srcs/sources_1/bd/video_cp/video_cp.bd

[Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.

I'm pretty sure my IP each pins are connected correctly. Does the composable pipeline vivado project can't be built by the GUI interface, and must use the tcl command?

[mariodruiz]

Hi,

This seems like a problem with your system language https://support.xilinx.com/s/question/0D52E00006iHkb3SAC/system-language-problem-with-commapoint-in-vivado?language=en_US

A mix between decimal and thousand separator. You should use English as your system language.

Mario

[Kgfu]

Hi, My Ubuntun system langue uses English now.

[mariodruiz]

Try to rebuild the project now, you may want to start from scratch. It is highly likely that the HLS IP were not generated properly before.

[Kgfu]

Hi, what't the scratch you mean here?

I rebuild the project and run the "Generation Bitstream" without any modification, the result is good. Once I modified anything, likes remove the colorthresholding_accel, the build error will happen as below: The error seems the FPGA resource is not enough for the design, it's very strange...

[mariodruiz]

I mean from scratch , start from 0.

Yes, I do not what the problem is. My suggestion would be to start from scratch as I mention, a fresh cloned repository. The fact that the HLS IP were generated with the previous system language could have something to do with this.

[Kgfu]

Hi Another question, if we want to replace the original bitstream, how can we do that?

According to the installation of steps:

1. python3 -m pip install PYNQ_Composable_Pipeline/ --no-build-isolation
2. pynq-get-notebooks pynq-composable -p $PYNQ_JUPYTER_NOTEBOOKS

Suppose the step 1 will call the setup.py and download latest bitstreams from below link for PYNQ-Z2: https://www.xilinx.com/bin/public/openDownload?filename=composable-video-pipeline-Pynq-Z2-v1_0_0.zip

It seems only unpack it to the overlay_dest, but doesn't have installation processing.

Can we just modify these code and use our built bitstream to replaced the download & unpack steps.

[mariodruiz]

You can put the bitstream and hwh files next to the notebooks. You do not need to use the setup script to deliver you custom composable overlay.

[Kgfu]

Thanks. I make thing more complicated...