Build synthesis error - Githubissues

Hi, I ran ./make-hw.sh W1A2 pynq a and got error bellow. My version of vivado is 2018.2. Can you help me? Thanks

`Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ERROR: [Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 60002 of such cell types but only 53200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning. ERROR: [Place 30-640] Place Check : This design requires more LUT as Memory cells than are available in the target device. This design requires 30417 of such cell types but only 17400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning. ERROR: [Place 30-640] Place Check : This design requires more LUT as Distributed RAM cells than are available in the target device. This design requires 29892 of such cell types but only 17400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning. ERROR: [Place 30-640] Place Check : This design requires more RAMS64E cells than are available in the target device. This design requires 19968 of such cell types but only 17400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 132c4f8d9

Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 3554.590 ; gain = 0.000 ; free physical = 3301 ; free virtual = 25181 Phase 1 Placer Initialization | Checksum: 132c4f8d9

Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 3554.590 ; gain = 0.000 ; free physical = 3300 ; free virtual = 25180 ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. Ending Placer Task | Checksum: 132c4f8d9

Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 3554.590 ; gain = 0.000 ; free physical = 3305 ; free virtual = 25185 INFO: [Common 17-83] Releasing license: Implementation 56 Infos, 21 Warnings, 0 Critical Warnings and 6 Errors encountered. place_design failed ERROR: [Common 17-69] Command failed: Placer could not place all instances INFO: [Common 17-206] Exiting Vivado at Fri Aug 24 14:17:56 2018... [Fri Aug 24 14:17:56 2018] impl_1 finished wait_on_run: Time (s): cpu = 00:07:18 ; elapsed = 00:10:54 . Memory (MB): peak = 1732.375 ; gain = 0.000 ; free physical = 3657 ; free virtual = 25537 INFO: [Common 17-206] Exiting Vivado at Fri Aug 24 14:17:56 2018... cp: cannot stat '/home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/vivado/W1A2-pynq/W1A2-pynq.runs/impl_1/procsys_wrapper.bit': No such file or directory cat: /home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/vivado/W1A2-pynq/W1A2-pynq.runs/impl_1/procsys_wrapper_timing_summary_routed.rpt: No such file or directory cat: /home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/vivado/W1A2-pynq/W1A2-pynq.runs/impl_1/procsys_wrapper_utilization_placed.rpt: No such file or directory cat: /home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/vivado/W1A2-pynq/W1A2-pynq.runs/impl_1/procsys_wrapper_utilization_placed.rpt: No such file or directory cat: /home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/vivado/W1A2-pynq/W1A2-pynq.runs/impl_1/procsys_wrapper_utilization_placed.rpt: No such file or directory Bitstream copied to /home/anhnt/QNN-MO-PYNQ/qnn/src/network/output/bitstream/W1A2-overlay-pynq.bit Done! `

Xilinx / QNN-MO-PYNQ

Build synthesis error #12