When attempting to use the output of DREAMPlaceFPGA, the site router in RapidWright must address a couple of additional details in order for the design to be read into Vivado and routed correctly. This tests for those details by routing the design in Vivado and checking the status of report_route_status afterwards to ensure that there are zero errors and that all nets are routed.
This also modifies the submodule GHA test to run regardless of the target branch of the PR.
When attempting to use the output of DREAMPlaceFPGA, the site router in RapidWright must address a couple of additional details in order for the design to be read into Vivado and routed correctly. This tests for those details by routing the design in Vivado and checking the status of
report_route_statusafterwards to ensure that there are zero errors and that all nets are routed.This also modifies the submodule GHA test to run regardless of the target branch of the PR.