Missing properties for DSP48E1?

I was running some tests with DSP48E1's using RapidWright, and there's something I don't understand. I have a test design which only contains 1 DSP48E1, and the properties that are listed are here:

PREG: integer(1)
USE_PATTERN_DETECT: string(NO_PATDET)
ADREG: integer(1)
IS_ALUMODE_INVERTED: string(4'b0000)
B_INPUT: string(DIRECT)
USE_SIMD: string(ONE48)
AREG: integer(1)
CREG: integer(1)
USE_MULT: string(MULTIPLY)
ALUMODEREG: integer(1)
MASK: string(48'h3FFFFFFFFFFF)
SEL_MASK: string(MASK)
DREG: integer(1)
CARRYINREG: integer(1)
PATTERN: string(48'h000000000000)
A_INPUT: string(DIRECT)
OPMODEREG: integer(1)
IS_INMODE_INVERTED: string(5'b00000)
SEL_PATTERN: string(PATTERN)
INMODEREG: integer(1)
MREG: integer(1)
USE_DPORT: boolean(false)
BOX_TYPE: string(PRIMITIVE)
BREG: integer(1)
ACASCREG: integer(1)
BCASCREG: integer(1)
IS_CLK_INVERTED: string(1'b0)
IS_CARRYIN_INVERTED: string(1'b0)
IS_OPMODE_INVERTED: string(7'b0000000)
AUTORESET_PATDET: string(NO_RESET)
CARRYINSELREG: integer(1)

It contains IS_x_INVERTED properties for the CLK, CARRYIN, ALUMODE, INMODE, and OPMODE. However, in another design I have, those properties aren't there:

PREG: integer(0)
USE_PATTERN_DETECT: string(NO_PATDET)
ADREG: integer(1)
METHODOLOGY_DRC_VIOS: string({SYNTH-10 {cell *THIS*} {string 18x18 4}})
B_INPUT: string(DIRECT)
USE_SIMD: string(ONE48)
AREG: integer(2)
CREG: integer(1)
USE_MULT: string(MULTIPLY)
ALUMODEREG: integer(0)
MASK: string(48'h3FFFFFFFFFFF)
SEL_MASK: string(MASK)
DREG: integer(1)
CARRYINREG: integer(0)
PATTERN: string(48'h000000000000)
A_INPUT: string(DIRECT)
OPMODEREG: integer(0)
SEL_PATTERN: string(PATTERN)
INMODEREG: integer(0)
MREG: integer(0)
USE_DPORT: boolean(false)
BREG: integer(0)
ACASCREG: integer(2)
BCASCREG: integer(0)
AUTORESET_PATDET: string(NO_RESET)
CARRYINSELREG: integer(0)

It's worth nothing that the DSP48E1 that does contain those properties was directly instantiated by me (although I didn't specify the IS_x_INVERTED properties), and the one without those properties was just inferred because the design used multiplication in some spots, and it's also worth noting that these properties are listed in the unisim library for DSP48E1's

https://github.com/Xilinx/XilinxUnisimLibrary/blob/1c8e05fd1e9a79ceb8b996a0996674122eed086f/verilog/src/unisims/DSP48E1.v#L57-L61

My question is why those properties only show in RapidWright for some DSP48E1's. As far as I knew, all instances of the same cell type will have the same properties each time, even though the values are different. In neither case are those specific properties directly set so they should all just be the default values. If you want to check it out yourself, I attached the files, and this is the python script I used to check the properties using RapidWright.

from bfasst import jpype_jvm
jpype_jvm.start()
from com.xilinx.rapidwright.design import Design, Cell

design = Design.readCheckpoint("", "") # dcp path, edf path
dsp_cell = design.getCell("") # u19/u14/u11/u8/Z_temp_110 for jpegencode.dcp, dsp48e1_inst for dsp48e1.dcp
properties = dsp_cell.getProperties()

for key, value in properties.items():
    print(key + ": " + str(value))

dsp_and_edf.zip

@reillymck

Xilinx / RapidWright

Missing properties for DSP48E1? #1013