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Build Customized FPGA Implementations for Vivado
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[Interchange] Device Resources Verifier Fixes #1014

Closed clavin-xlnx closed 3 months ago

clavin-xlnx commented 3 months ago

Fixes three main issues with verifying an XCVP1902 device when exporting via the FPGA Interchange Format:

  1. Fixes redundant reading in loops of site pins during verification that led to a Cap'n Proto "Read limit exceeded" message.
  2. Removes the unused macros in the reference library in the same manner as when they are removed to be written out. This was causing a mismatch previously.
  3. Skips constant verification if the routing information is not present.