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Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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Report Timing Example: Build Failed #1109

Closed EirGalid closed 1 week ago

EirGalid commented 2 weeks ago

Hello, I'm facing an issue when I try to run the Report Timing Example with a dcp file that I've generated. I'm currently using Java 17.0.12, gradle is on version 7.4.2 and my Vivado version is 2023.2. Documentation states that the versions are compatible. I'm not sure if I should downgrade my Vivado version or not.

Screenshot 2024-11-19 135859

clavin-xlnx commented 2 weeks ago

Thanks for posting the stack trace. Unfortunately, I can't determine the exact cause of the failure with out having an example design. Would you be able to share a DCP that triggers this error? What part is the design targeting? Is your design fully placed?

One thing to note is that the timing model only support UltraScale+ devices currently.

EirGalid commented 2 weeks ago

Thank you for your answer. I was using DCP files generated from a Zybo Z7-10 board. I'll troubleshoot it a bit more and will come back if there is any other issue.

Regarding the DCP that triggers the error, could originate from a very simple circuit (for example an adder) to FSM implementations. Whatever design I tried failed. But as I said, I only tried on Z7-10.