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Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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Timing-Driven Routing Issue & Potential Bug in PipelineGeneratorWithRouting #111

Closed Licheng-Guo closed 3 years ago

Licheng-Guo commented 3 years ago

Hi Chris,

I wonder if RW will provide a timing-driven router? Seems that only a non-timing-driven one is available currently.

Meanwhile, I tried the timing-driven routing routine in the PipelineGeneratorWithRouting example and I found two issues:

1) the routing is very slow. On our server, it takes 20+ seconds to route one net. Basically the watchdog expires every time. From the description of the algorithm, it seems to me that the router will not terminate even if it has found a solution within the user-specified timing target, but will continue to exhaust the solution space. Not sure if this causes the process to be slow.

=>Quote from the document: "We terminate the loop when we have either: (a) exhausted the candidate next hops as not feasible or (b) when the watchdog timer expires."

2) the final results contain routing conflicts. In my test, I simply change the width to 16 and set the target frequency as 333MHz, and keep other parameters as default. Is it the case that each invocation of findRoute() is independent, so the results may conflict?

Thanks for your help!

Best, Licheng

clavin-xlnx commented 3 years ago

Hi Licheng,

Thank you for reaching out. We are working on a robust timing-driven router that will become part of RapidWright in a few months. The example you are using was written in mind for demonstration purposes and not necessarily for high performance or fast runtime.

Although the router is not quite ready for release, if you are interested in working with us as an alpha tester, please reach out to me directly. We are interested in engaging the research community, so happy to explore synergies with your current project.

Thanks,

Chris