Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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Site.getIntTile() produces ArrayIndexOutOfBoundsException #29

Closed cfib closed 5 years ago

cfib commented 5 years ago

Site.getIntTile() produces ArrayIndexOutOfBoundsException in line 4 with this Python code xc7a35t_getIntTile.py

I executed RapidWright as follows: java -jar /opt/Xilinx/rapidwright/jars/rapidwright-2018.3.2-standalone-lin64.jar xc7a35t_getIntTile.py.txt

This is the generated traceback: traceback_getIntTile.txt

clavin-xlnx commented 5 years ago

Thank you for the bug. It looks like this method was not implemented with Series 7 devices in mind. I will plan on adding support in the next release. For now, you can try using this work-around code for SLICEs in Series 7 devices:

public static Tile getIntTile(Site s) {
    int wire = s.getTileWireIndexFromPinName("CLK");
    Node n = new Node(s.getTile(),wire);
    for(Wire w : n.getAllWiresInNode()){
        if(Utils.isSwitchBox(w.getTile().getTileTypeEnum())){
            return w.getTile();
        }
    }
    for(PIP p : n.getTile().getBackwardPIPs(wire)){
        Wire w = p.getStartWire();
        for(Wire w2 : w.getNode().getAllWiresInNode()){
            if(Utils.isSwitchBox(w2.getTile().getTileTypeEnum())){
                return w2.getTile();
            }
        }
    }
    return null;
}
daveshah1 commented 5 years ago

FYI, I am also seeing a similar exception for certain types of Sites (such as IOBs, which as far as I can tell should have a valid interconnect tile) on the UltraScale+

Minimum test case example:

package dev.fpga.rapidwright;

import com.xilinx.rapidwright.device.Device;

public class bug2 {
    public static void main(String[] args) {
        Device d = Device.getDevice("xczu2cg-sbva484-1-e");
        d.getSite("IOB_X0Y130").getIntTile();
    }
}
clavin-xlnx commented 5 years ago

This should be fixed in 2019.1.0, please reopen if there are further issues.