search

Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
Other
284 stars 109 forks source link

ERROR: Don't know net of RAMB18_X0Y44/RDCLK #31

Closed Db2515 closed 5 years ago

Db2515 commented 5 years ago

I am trying to create a Module from a checkpoint file and metadata generated for an component that has been implemented out of context. However during I get the following Exception: Exception in thread "main" java.lang.RuntimeException: ERROR: Don't know net of RAMB18_X0Y44/RDCLK at com.xilinx.rapidwright.design.MetadataParser.parse(MetadataParser.java:361) at com.xilinx.rapidwright.design.Module.(Unknown Source) at DottyStitcher.loadModule(DottyStitcher.java:136) at DottyStitcher.main(DottyStitcher.java:157)

I am trying generate a design for the Basys 3 board (part namexc7a35tcpg236-1) and code for the component I am using can be found here: https://github.com/Db2515/FPGA_Rapid_Render/tree/VGA/components/VGA_output

And I have attached the checkpoint and metadata files out.tar.gz

Please let me know if you require anymore details

Cheers,

Daniel

clavin-xlnx commented 5 years ago

Hi Daniel,

The problem occurs in that some sites in our devices will support more than one type of functionality (primary type vs. alternate types). Sometimes, pin names can differ for for an alternate type if it is used and a lookup was failing during the parsing of the metadata. I committed a fix to support alternate site types and was able to resolve the error you reported (See d59e181).

Thanks for reporting the issue.

Chris