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Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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Release 2019.1.2 fails in the Pre-Implemented Module Flow #53

Closed Licheng-Guo closed 4 years ago

Licheng-Guo commented 4 years ago

Hi Chris,

When running the default "Build an IP Integrator Design with Pre-Implemented Blocks" tutorial using both the standalone jar and the auto-installed jar of version 2019.1.2, the process will error out in the middle, when calling the ipi.BlockStitcher after the util.jobQueue finishes:

Exception in thread "main" java.lang.RuntimeException: ERROR: Couldn't identify parent net, no output pins (or top level output port) found. at com.xilinx.rapidwright.edif.EDIFNetlist.getNetAliases(EDIFNetlist.java:874) at com.xilinx.rapidwright.edif.EDIFNetlist.generateParentNetMap(EDIFNetlist.java:946) at com.xilinx.rapidwright.edif.EDIFNetlist.getParentNetMap(EDIFNetlist.java:892) at com.xilinx.rapidwright.ipi.BlockStitcher.stitchDesign(BlockStitcher.java:145) at com.xilinx.rapidwright.ipi.BlockStitcher.main(BlockStitcher.java:583)

However, we could successfully pass through if using the 2018.3.3 release of the standalone jar. Do you know the potential problem with the situation?

Thanks for your help!

clavin-xlnx commented 4 years ago

Thank you for opening this issue, I have recently learned of this issue and I am working on a fix currently.

clavin-xlnx commented 4 years ago

I have just committed a change that should resolve this issue. When the update was made to support macro primitives, EDIFCell.isPrimitive() APIs must have changed behavior just enough to cause traversal of netlists with blackboxes to behave differently.

I created a new API that is more explicit (EDIFCell.isLeafCellOrBlackBox()) that is used instead.

Licheng-Guo commented 4 years ago

Thanks for your help!