Closed jakobwenzel closed 1 year ago
@jakobwenzel Thanks for reporting this. A fix should be in the new branch 2022.2.1
, give it a try and let us know if there is anything else amiss.
Thanks for the quick fix! I've tried it with some bigger designs and it works perfectly.
Should we leave this issue open until 2022.2.1 is merged or close it now?
Closing, as #606 is merged now.
RapidWright seems to parse this Vivado 2022.2 DCP incorrectly. The names of cells and nets located at deeper levels of hierarchy are incorrect. For cells, corruption seems to start at the second level, while for nets it seems to start at the third.
When writing the design back to disk, RapidWright produces a corrupted DCP. Vivado can no longer read placement/routing of affected cells/nets.
The DCP contains these cells (corrupted names in bold):
Regenerating the DCP (collapsed)
Save this as `design.v`: ```verilog module testing #(parameter DEPTH=3) (input wire i, output wire o, input wire clk); reg r; always @(posedge clk) r <= i; generate if (DEPTH<=1) begin assign o=r; end else begin testing #(DEPTH-1) inst(r, o, clk); end endgenerate endmodule ``` Run these commands in Vivado: ```tcl read_verilog design.v synth_design -mode out_of_context -top testing -part XC7A200T-SBG484-1 -flatten_hierarchy none place_design route_design write_checkpoint -force design.dcp write_edif -force design.edf ``` This minimal example uses `-flatten_hierarchy none` to preserve hierarchy. On larger designs, I've seen this issue occur without the flag. RapidWright code: ```java Design design = Design.readCheckpoint(args[0], args[1]); design.writeCheckpoint("saveAgain.dcp"); System.out.println("cells"); for (Cell cell : design.getCells()) { System.out.println(cell.getName()); } System.out.println("\nnets"); for (Net net : design.getNets()) { if (!net.isStaticNet() && !net.getName().equals(Net.USED_NET)) { System.out.println(net.getName()); } } ```