Closed nqdtan closed 10 months ago
I have found a workaround to avoid the naming collision of encrypted cells, in particulars those involving Xilinx floating point IPs. Basically, I need to enable the option of generating synthesized checkpoints for these IPs in Vivado:
set_property generate_synth_checkpoint true [get_files cl_linear_fadd_32ns_32ns_32_3_primitive_dsp_1_ip.xci]
This will enforce Vivado to prepend the module name cl_linear_fadd_32ns_32ns_32_3_primitive_dsp_1_ip
to the encrypted cell name. Therefore, we get something like this in the final design checkpoint
With this, I should be able to distinguish the encrypted cells from different designs.
One other thing that might be useful in mitigating this issue is the Vivado Tcl command rename_ref
:
rename_ref -help
rename_ref
Description:
rename a cell ref
Syntax:
rename_ref [-ref <arg>] [-to <arg>] [-prefix_all <arg>] [-quiet] [-verbose]
Usage:
Name Description
--------------------------
[-ref] Cell ref to rename
[-to] New name
[-prefix_all] Rename all eligible hierarchical cell refs in the current
design. Construct the new name using the given prefix plus
the original name
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
Categories:
Netlist
Description:
Rename the reference name of a single non-primitive cell, or apply a
reference prefix to all non-primitive cells in the current synthesized or
implemented design.
This command provides a mechanism to change the non-primitive reference
names in the current design so that they do not collide with the reference
names in another design. This lets two modules or designs be synthesized or
simulated together, while avoiding any name collisions between the two
designs.
This command returns nothing when renaming the reference a single cell, and
returns the number of cells renamed when used with -prefix_all. If the
command fails, an error is returned.
Awesome!
Please find the relevant checkpoint and EDIF files attached. My code is as follows
Here, I attempt to combine the two designs
socket0
andsocket1
usingModuleInst
. They have some common cells, and they are produced from the same flow separately. I have added some prefixes to avoid naming conflicts. When I loaded the checkpoint in Vivado using the generatednew_top_design_load.tcl
, I got the following errorwhich is not surprising because the encrypted cells (
floating_point_*
) also got renamed as well, so they did not match the cells defined in the existing encrypted*.edn
files located incheckpoints/socket0/*.edn
andcheckpoints/socket1/*.edn
.On the other hand, some encrypted cells between the two designs share similar names, but have different interfaces, so I cannot simply unify these cells to the same name. For example, as shown in the following screenshots,
checkpoints/socket0/floating_point_v7_1_15__parameterized1.edn
refers tofcmp_32
op indesign0
, whilecheckpoints/socket1/floating_point_v7_1_15__parameterized1.edn
refers tofadd_32
op indesign1
.Do you have any advice on how to solve this issue? Thanks!
merge_issue.zip