Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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How to use outmuxa? #873

Closed the-centry closed 8 months ago

the-centry commented 8 months ago

How to use the outmux(a|b|c|d) while create a cell? Thanks so much!

the-centry commented 8 months ago

WARNING: Could not find parent of net "CLEL_R_X73Y0.CLE_CLE_L_SITE_0_A_O.HPIO_L_X71Y180.HPIO_IOBPAIR_72_OP_PIN", please check that the netlist is fully connected through all levels of hierarchy for this net.

clavin-xlnx commented 8 months ago

How to use the outmux(a|b|c|d) while create a cell? Thanks so much!

package com.xilinx.rapidwright.examples;

import com.xilinx.rapidwright.design.Cell;
import com.xilinx.rapidwright.design.Design;
import com.xilinx.rapidwright.design.Net;
import com.xilinx.rapidwright.design.SitePinInst;
import com.xilinx.rapidwright.design.Unisim;
import com.xilinx.rapidwright.device.BELPin;
import com.xilinx.rapidwright.rwroute.RWRoute;

public class LUT1Example {

    public static void main(String[] args) {
        Design design = new Design("example", "xcvu3p-ffvc1517-1-i");
        Cell cell = design.createAndPlaceCell("lut1", Unisim.LUT1, "SLICE_X18Y31/A6LUT");
        cell.addProperty("INIT", "O=I0");
        Net net = design.createNet("net0");
        net.connect(cell, "O");
        net.connect(cell, "I0");
        // By default, it will use the A_O output pin, so we'll remove it and use AMUX
        // instead to force the use of OUTMUXA
        net.removeSource();
        SitePinInst outputPin = net.createPin("AMUX", cell.getSiteInst());
        BELPin lutOutput = cell.getBEL().getPin("O6");
        // Route the intra-site connection
        cell.getSiteInst().routeIntraSiteNet(net, lutOutput, outputPin.getBELPin());
        // Route the inter-site connection
        RWRoute.routeDesignFullNonTimingDriven(design);
        design.writeCheckpoint("example.dcp");
    }
}

This will force the use of the OUTMUX as shown in this routed view in Vivado: image

clavin-xlnx commented 8 months ago

WARNING: Could not find parent of net "CLEL_R_X73Y0.CLE_CLE_L_SITE_0_A_O.HPIO_L_X71Y180.HPIO_IOBPAIR_72_OP_PIN", please check that the netlist is fully connected through all levels of hierarchy for this net.

This means there is an inconsistency in the created logical netlist. You may have a logical net name that is inconsistent with the physical net name.

the-centry commented 8 months ago

WARNING: Could not find parent of net "CLEL_R_X73Y0.CLE_CLE_L_SITE_0_A_O.HPIO_L_X71Y180.HPIO_IOBPAIR_72_OP_PIN", please check that the netlist is fully connected through all levels of hierarchy for this net.

This means there is an inconsistency in the created logical netlist. You may have a logical net name that is inconsistent with the physical net name.

Whether it means I need connect the cell and sitepin while create a cell instance!