Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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[DesignTools.makeBlackBox()] Fix for #967 #970

Closed clavin-xlnx closed 3 months ago

clavin-xlnx commented 3 months ago

When preparing a design to create a black box and ensure that the routing of the surrounding logic remains intact, sometimes the tool will attempt to insert a LUT1 as a way to preserve existing routing. #967 stumbled on a bug where the tool found a scenario that fit the criteria for inserting a LUT1, but was not actually necessary as the source of the FF routing was actually internal to the SLICE (a GND post available for only AFF and AFF2 as shown in this picture:

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