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Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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[RWRoute,PhysNetlistReader] Set logical driver on PIPs #973

Closed eddieh-xlnx closed 3 months ago

eddieh-xlnx commented 3 months ago

For nets with multiple source pins (e.g. A_O and AMUX) set the logical driver flag on the first PIP leaving the primary source.