Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
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[RWRoute] Fix logical driver flag setting for DCP write #979

Closed clavin-xlnx closed 3 months ago

clavin-xlnx commented 3 months ago

The DCP writer depends on nets with a logical driver flag (used only for nets that use multiple site output pins for the same logical routing tree) to be the first source PIP in the list of pips on the Net. These changes modify the addition of this flag in RWRoute such that it adheres to this convention.

eddieh-xlnx commented 3 months ago

Fixes issue introduced by #973