Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
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Alveo U250 DSP48E2_{X28|X29} cell: <LOCKED>(BEL: (unplaced)) #986

Closed RipperJ closed 2 months ago

RipperJ commented 2 months ago

Hi. When using DesignTools.calculateUtilization(...) on a design implemented on Alveo U250, the two columns of DSPs on the right side (beside the Vitis default static region) are locked and hence triggers exceptions in public static Map<UtilizationType, Integer> calculateUtilization(Collection<SiteInst> siteInsts), when c.getBELName() is found null.

clavin-xlnx commented 2 months ago

Thank you for reporting this issue, please give #988 a try, it should resolve the NPE.

RipperJ commented 2 months ago

Yes #988 resolves this issue. Thanks.