Closed definelicht closed 7 years ago
the parameters we used are 64 64 64
Does that translate to a 64x64 matrix? Does it not support larger matrices? Or does this relate to the hardware buffer?
It would be very useful if you could add some documentation on the input parameters :-)
EDIT: 64 64 64 works for me, but any other parameters cause the test to fail.
Will ask the team who wrote the kernel to add some documentation on this.
limitations on parameters:
The three upper bounds you listed are not multiples of 32/64, so I suppose it should be strictly lower than?
The kernel does not verify for me for any other parameters than 64 64 64. 128 128 64 yields wrong results. Is this expected?
Could the developers also provide the source files for kernels? As a newbie for SDAccel tools, I encountered several device does not match issues. Maybe I want to try to compile the kernel parts myself. Thanks.
BTW, how to put two kernel functions into one program using C/C++ rather than OpenCL? Or are the kernelSgemm_0 and kernelSgemm_1 C/C++ or OpenCL kernels?
Hi @definelicht and @troore we will get back to your question. I can answer @troore quesiton: how to put two kernel functions into one program using C/C++ rather than OpenCL? Please refer below example ( it has two C/C++ kernels inside single binary container): https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/kernel_opt/loop_perfect_c
hi @troore @definelicht , we can't provide source code for it. It is provided as a block and is encrypted.
I tried the parameters other than 64 64 64, e.g. 128 128 64 it works on my system. I guess it is the issue of the sdaccel set up that causes the failure.
@definelicht I too have not been able to reproduce this issue. Please email me with further questions.
@troore This is an RTL kernel optimized for the xil-accel-rd-ku115:4ddr-xpr device. Please search/post in the Xilinx SDAccel forums for help with your SDAccel environment setup. For general SDAccel questions please refer to the SDAccel docs. Regarding your C/C++ question see the SDAccel docs page here
Verification of
acceleration/gemm
fails on xilinx:xil-accel-rd-ku115:4ddr-xpr:4.0 with SDx 2017.1.Example execution below:
Steps to reproduce:
make all TARGETS=hw
.LD_LIBRARY_PATH=/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64 /gemm 4096 4096 54
Installed DSA: xilinx:xil-accel-rd-ku115:4ddr-xpr:4.0
Other kernels execute correctly.
What are the acceptable parameters for rows, cols and depth, and what is the effect of depth? Perhaps put this in the readme?