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Xilinx / SDSoC-Tutorials

SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
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Warnings in Lab3 while building sdx_app1 #20

Open peter2chang opened 5 years ago

peter2chang commented 5 years ago

Hi, I got 2 warnings while building the sdx_app1 in lab 3, do you know what seem to be the issues? I am using zedboard as target board, so there were some modifications made for zedboard as I followed along the tutorials. The build was completed and output files in sd_card folder can be run on my zedboard and output was seen via terminal program. Thank you.

1) WARNING: [CF2XD 83-1006] Invalid clock id 1 for platform zedboard clock_id

2) CRITICAL WARNING: [VPL 60-724] 'D:/SDSoC_projects/sdx_workspace/zedboard/export/zedboard/hw/zedboard.dsa' : failed DSA integrity check: digest mismatch. DSA

sgrace-xlnx commented 5 years ago

The digest message can be ignored (that usually tells us that the DSA file was unzipped and re-zipped, which is not in this case). Depending on what version of the tool you're using, this should be addressed in the latest release of the tool.

The invalid clock ID all depends on what is set to default values of the ID. In this case, the tool did not find the default clock of id 1. This usually means that in the DSA, there is no clock id 1, and the default being set to 1 caused this issue.