Question regarding Clocking Wizard IP reset type in “SDSoC Platform Creation Labs > Lab 1”

Xilinx / SDSoC-Tutorials

SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials

146 stars 53 forks source link

Question regarding Clocking Wizard IP reset type in “SDSoC Platform Creation Labs > Lab 1” #23

Open peter2chang opened 5 years ago

peter2chang commented 5 years ago

In lab1 step2 (create an IP Integrator Design), Clocking Wizard IP’s reset type is set to active low. Is it because the Zynq7 SoC is used? Should I need to set reset type to Low for all my projects that use Zynq7 in the future? Thanks in advance!