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Xilinx / Vitis-AI-Tutorials

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Timing Failure in Vitis Build #3

Open dnicholes opened 4 years ago

dnicholes commented 4 years ago

Bitstream Generation fails to complete with the error:

VPL-4: design did not meet timing - Design failed to meet timing.

Error from the Vivado (v2019.2.1) build log:

ERROR: [runtcl-1] design did not meet timing - Design failed to meet timing. Failed timing checks (paths): {ultra96v2_mipi_i/dpu_xrt_top_1/inst/u_631818d4/m_43dd20ae/u_b2263e3b/s_189e67da_reg[0]/C --> ultra96v2_mipi_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]/D}