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Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
https://www.xilinx.com/ai
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vitis-ai 3.0 pytorch quantize failed: list index out of range #1291

Open takeshiho0531 opened 1 year ago

takeshiho0531 commented 1 year ago

Hi. I'd like to quantize SSD by using xilinx/vitis-ai-pytorch-cpu:ubuntu2004-3.0.0.106 Docker image, but I got an error saying "IndexError: list index out of range." 

python ssd_quant.py --quant_mode float --inspect --batch_size 1 --target DPUCZDX8G_ISA1_B1024
Traceback (most recent call last):
  File "ssd_quant.py", line 157, in <module>
    file_path=file_path)
  File "ssd_quant.py", line 111, in quantization
    inspector.inspect(quant_model, (input,), device=device)
  File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/pytorch_nndct/apis.py", line 196, in inspect
    self._inspector_impl.inspect(module, input_args, device, output_dir, verbose_level)
  File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/pytorch_nndct/hardware_v3/inspector.py", line 53, in inspect
    self._device_allocator.process(dev_graph)
  File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/nndct_shared/inspector/device_allocator.py", line 36, in process
    self._post_process(graph)
  File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/nndct_shared/inspector/device_allocator.py", line 134, in _post_process
    pn = graph.parents(node)[0]
IndexError: list index out of range

Here's the detail log:

log ``` (vitis-ai-pytorch) vitis-ai-user@docker-desktop:/workspace/src/vai_quantizer/vai_q_pytorch/example$ python ssd_quant.py --quant_mode float --inspect --batch_size 1 --target DPUCZDX8G_ISA1_B1024 No CUDA runtime is found, using CUDA_HOME='/usr/local/cuda' [VAIQ_NOTE]: Loading NNDCT kernels... -------- Start ssd300 test [VAIQ_NOTE]: Inspector is on. [VAIQ_NOTE]: =>Start to inspect model... [VAIQ_NOTE]: =>Quant Module is in 'cpu'. [VAIQ_NOTE]: =>Parsing SSD... [VAIQ_NOTE]: Start to trace and freeze model... [VAIQ_NOTE]: The input model SSD is torch.nn.Module. [VAIQ_NOTE]: Finish tracing. [VAIQ_NOTE]: Processing ops... ██████████████████████████████████████████████████| 130/130 [00:00<00:00, 836.67it/s, OpInfo: name = return_0, type = Return] [VAIQ_WARN][QUANTIZER_TORCH_FLOAT_OP]: The quantizer recognize new op `nndct_expand_as` as a float operator by default. [VAIQ_WARN][QUANTIZER_TORCH_FLOAT_OP]: The quantizer recognize new op `aten::pow` as a float operator by default. [VAIQ_WARN][QUANTIZER_TORCH_FLOAT_OP]: The quantizer recognize new op `aten::sqrt` as a float operator by default. [VAIQ_NOTE]: =>Doing weights equalization... [VAIQ_NOTE]: =>Quantizable module is generated.(quantize_result/SSD.py) [VAIQ_WARN]: SSD::2904 is not tensor. [VAIQ_WARN]: SSD::2911 is not tensor. [VAIQ_WARN]: SSD::2918 is not tensor. [VAIQ_WARN]: SSD::2925 is not tensor. [VAIQ_WARN]: SSD::2932 is not tensor. [VAIQ_WARN]: SSD::2939 is not tensor. [VAIQ_WARN]: SSD::2949 is not tensor. [VAIQ_WARN]: SSD::2956 is not tensor. [VAIQ_WARN]: SSD::2963 is not tensor. [VAIQ_WARN]: SSD::2970 is not tensor. [VAIQ_WARN]: SSD::2977 is not tensor. [VAIQ_WARN]: SSD::2984 is not tensor. [VAIQ_WARN]: SSD::2994 is not tensor. [VAIQ_WARN]: SSD::3002 is not tensor. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[14]/input.27, op type:nndct_conv2d, output shape: [1, 75, 75, 256] node name:SSD::SSD/ReLU[vgg]/ModuleList[15]/2196, op type:nndct_relu, output shape: [1, 75, 75, 256] WARNING: Logging before InitGoogleLogging() is written to STDERR I20230715 00:23:15.193228 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.193437 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.193583 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.194012 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_2ZfJbXe7lt0NdQ3g, with op num: 9 I20230715 00:23:15.194097 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.249791 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.249948 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[0]/2437, op type:nndct_conv2d, output shape: [1, 19, 19, 256] node name:SSD::SSD/input.63, op type:nndct_relu, output shape: [1, 19, 19, 256] I20230715 00:23:15.256254 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.256328 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.256345 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.256564 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_3EDNJcuoTxqa4eLZ, with op num: 9 I20230715 00:23:15.256640 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.284181 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.284309 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[12]/input.23, op type:nndct_conv2d, output shape: [1, 75, 75, 256] node name:SSD::SSD/ReLU[vgg]/ModuleList[13]/input.25, op type:nndct_relu, output shape: [1, 75, 75, 256] I20230715 00:23:15.291505 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.291582 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.291599 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.291700 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_hSK7UTCqmbQczgOL, with op num: 9 I20230715 00:23:15.291769 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.341579 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.341706 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[4]/2517, op type:nndct_conv2d, output shape: [1, 5, 5, 128] node name:SSD::SSD/input.71, op type:nndct_relu, output shape: [1, 5, 5, 128] I20230715 00:23:15.346865 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.346957 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.346979 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.347203 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_BgbI0XyG1LoFrA7Q, with op num: 9 I20230715 00:23:15.347280 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.360213 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.360321 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[1]/2457, op type:nndct_conv2d, output shape: [1, 10, 10, 512] node name:SSD::SSD/input.65, op type:nndct_relu, output shape: [1, 10, 10, 512] I20230715 00:23:15.368171 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.368325 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.368388 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.368531 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_qU6ypE10SusH3rmi, with op num: 9 I20230715 00:23:15.368633 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.453292 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.453408 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[5]/2537, op type:nndct_conv2d, output shape: [1, 3, 3, 256] node name:SSD::SSD/input.73, op type:nndct_relu, output shape: [1, 3, 3, 256] I20230715 00:23:15.459656 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.459733 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.459764 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.460952 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_v0W2Lm1gjOt5aI3F, with op num: 9 I20230715 00:23:15.460981 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.492352 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.492462 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[19]/input.35, op type:nndct_conv2d, output shape: [1, 38, 38, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[20]/input.37, op type:nndct_relu, output shape: [1, 38, 38, 512] I20230715 00:23:15.505371 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.505494 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.505512 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.505614 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_RNfsrZlA3ypTKukw, with op num: 9 I20230715 00:23:15.505652 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.667171 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.667272 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[2]/2477, op type:nndct_conv2d, output shape: [1, 10, 10, 128] node name:SSD::SSD/input.67, op type:nndct_relu, output shape: [1, 10, 10, 128] I20230715 00:23:15.672199 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.672268 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.672284 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.672420 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_YKPULHeihfb7XWTF, with op num: 9 I20230715 00:23:15.672469 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.685834 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.685989 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[28]/input.51, op type:nndct_conv2d, output shape: [1, 19, 19, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[29]/2364, op type:nndct_relu, output shape: [1, 19, 19, 512] I20230715 00:23:15.696067 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.696146 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.696189 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.696327 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_SgR8GFclmONMV76H, with op num: 9 I20230715 00:23:15.696379 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.862668 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.862776 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[33]/input.59, op type:nndct_conv2d, output shape: [1, 19, 19, 1024] node name:SSD::SSD/ReLU[vgg]/ModuleList[34]/input.61, op type:nndct_relu, output shape: [1, 19, 19, 1024] I20230715 00:23:15.872660 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.872745 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.872799 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.872964 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_IRc0dqsmMSHK8Vk4, with op num: 9 I20230715 00:23:15.873030 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.951483 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.951597 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[0]/input.3, op type:nndct_conv2d, output shape: [1, 300, 300, 64] node name:SSD::SSD/ReLU[vgg]/ModuleList[1]/input.5, op type:nndct_relu, output shape: [1, 300, 300, 64] I20230715 00:23:15.956288 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.956399 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.956497 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.956662 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_hRqtKN4A5pCMx7WY, with op num: 9 I20230715 00:23:15.956712 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:15.965895 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:15.966001 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[17]/input.31, op type:nndct_conv2d, output shape: [1, 38, 38, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[18]/input.33, op type:nndct_relu, output shape: [1, 38, 38, 512] I20230715 00:23:15.973728 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:15.973815 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:15.973834 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:15.973935 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_Am0ncCwIZX27Dvib, with op num: 9 I20230715 00:23:15.973997 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.075985 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.076129 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[2]/input.7, op type:nndct_conv2d, output shape: [1, 300, 300, 64] node name:SSD::SSD/ReLU[vgg]/ModuleList[3]/2068, op type:nndct_relu, output shape: [1, 300, 300, 64] I20230715 00:23:16.084214 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.084308 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.084347 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.084476 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_ABYOEXetoMCbU4rv, with op num: 9 I20230715 00:23:16.084514 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.096154 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.096249 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[7]/input.15, op type:nndct_conv2d, output shape: [1, 150, 150, 128] node name:SSD::SSD/ReLU[vgg]/ModuleList[8]/2122, op type:nndct_relu, output shape: [1, 150, 150, 128] I20230715 00:23:16.104148 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.104234 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.104281 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.104421 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_SwEHF86gqlvZCdWA, with op num: 9 I20230715 00:23:16.104466 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.124305 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.124445 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[5]/input.11, op type:nndct_conv2d, output shape: [1, 150, 150, 128] node name:SSD::SSD/ReLU[vgg]/ModuleList[6]/input.13, op type:nndct_relu, output shape: [1, 150, 150, 128] I20230715 00:23:16.130422 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.130496 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.130513 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.130610 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_cVrSDmR9IAtwqzYP, with op num: 9 I20230715 00:23:16.130678 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.145673 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.145779 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[24]/input.43, op type:nndct_conv2d, output shape: [1, 19, 19, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[25]/input.45, op type:nndct_relu, output shape: [1, 19, 19, 512] I20230715 00:23:16.157852 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.157939 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.157958 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.158059 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_85TWAy3DK0SuqMNV, with op num: 9 I20230715 00:23:16.158107 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.326632 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.326737 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[6]/2557, op type:nndct_conv2d, output shape: [1, 3, 3, 128] node name:SSD::SSD/input.75, op type:nndct_relu, output shape: [1, 3, 3, 128] I20230715 00:23:16.331405 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.331465 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.331501 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.331689 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_RKthn9Fgy2bjzLCc, with op num: 9 I20230715 00:23:16.331789 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.342878 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.342989 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[26]/input.47, op type:nndct_conv2d, output shape: [1, 19, 19, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[27]/input.49, op type:nndct_relu, output shape: [1, 19, 19, 512] I20230715 00:23:16.355587 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.356148 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.356176 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.356304 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_SEZLPhBxA3aI0yjc, with op num: 9 I20230715 00:23:16.356324 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.565959 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.566093 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[10]/input.19, op type:nndct_conv2d, output shape: [1, 75, 75, 256] node name:SSD::SSD/ReLU[vgg]/ModuleList[11]/input.21, op type:nndct_relu, output shape: [1, 75, 75, 256] I20230715 00:23:16.572712 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.572785 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.572803 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.572914 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_0JFcXuIjlstqKZMx, with op num: 9 I20230715 00:23:16.572953 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.602192 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.602326 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[31]/input.55, op type:nndct_conv2d, output shape: [1, 19, 19, 1024] node name:SSD::SSD/ReLU[vgg]/ModuleList[32]/input.57, op type:nndct_relu, output shape: [1, 19, 19, 1024] I20230715 00:23:16.618613 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.618739 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.618760 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.618952 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_qmbVCva5Nufw8yWl, with op num: 9 I20230715 00:23:16.619024 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.884567 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.884671 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[7]/2577, op type:nndct_conv2d, output shape: [1, 1, 1, 256] node name:SSD::SSD/input, op type:nndct_relu, output shape: [1, 1, 1, 256] I20230715 00:23:16.890182 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.890293 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.890352 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.890508 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_uM5nJNrPCZdH1VL0, with op num: 9 I20230715 00:23:16.890569 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.925347 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.925468 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[extras]/ModuleList[3]/2497, op type:nndct_conv2d, output shape: [1, 5, 5, 256] node name:SSD::SSD/input.69, op type:nndct_relu, output shape: [1, 5, 5, 256] I20230715 00:23:16.930671 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.930756 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.930801 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.931331 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_8xpY6J1kiZuDGROP, with op num: 9 I20230715 00:23:16.931878 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:16.961278 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:16.961443 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_18: node name:SSD::SSD/Conv2d[vgg]/ModuleList[21]/input.39, op type:nndct_conv2d, output shape: [1, 38, 38, 512] node name:SSD::SSD/ReLU[vgg]/ModuleList[22]/2270, op type:nndct_relu, output shape: [1, 38, 38, 512] I20230715 00:23:16.973943 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:16.974131 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:16.974148 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:16.974251 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_nndct_relu_1ubS2qjyGA7h8xQd, with op num: 9 I20230715 00:23:16.974296 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.153213 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.153340 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/ReLU[vgg]/ModuleList[22]/2270_sink_transpose_0, op type:nndct_permute, output shape: [1, 512, 38, 38] I20230715 00:23:17.200457 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.200556 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.200613 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.200873 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_permute_YHsIEjLQrCToX9Wb, with op num: 4 I20230715 00:23:17.201022 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... W20230715 00:23:17.209437 25772 PartitionPass.cpp:3741] [UNILOG][WARNING] xir::Op{name = SSD__SSD_ReLU_vgg__ModuleList_22__2270_sink_transpose_0, type = transpose} has been assigned to CPU. I20230715 00:23:17.209715 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 2, DPU subgraph number 0 I20230715 00:23:17.209805 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/L2Norm[L2Norm]/2282_sink_transpose_1, op type:nndct_permute, output shape: [1, 512, 38, 38] I20230715 00:23:17.213760 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.213819 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.213862 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.214015 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_permute_nlP4uiSMcV2NEqAm, with op num: 4 I20230715 00:23:17.214066 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... W20230715 00:23:17.220100 25772 PartitionPass.cpp:3741] [UNILOG][WARNING] xir::Op{name = SSD__SSD_L2Norm_L2Norm__2282_sink_transpose_1, type = transpose} has been assigned to CPU. I20230715 00:23:17.220381 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 2, DPU subgraph number 0 I20230715 00:23:17.220438 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2923, op type:nndct_reshape, output shape: [1, 2400] I20230715 00:23:17.224997 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.225071 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.225111 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.225215 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_Eocq8hXjLskZpwHI, with op num: 7 I20230715 00:23:17.225271 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.229786 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.229893 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/3000, op type:nndct_reshape, output shape: [1, 8732, 4] I20230715 00:23:17.234184 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.234285 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.234309 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.234436 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_jJfO4a9vY1zZDFNg, with op num: 8 I20230715 00:23:17.234493 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.240489 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.240658 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/3008, op type:nndct_reshape, output shape: [1, 8732, 4] I20230715 00:23:17.244983 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.245076 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.245093 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.245258 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_qbVSRAiLmMZg4u6w, with op num: 8 I20230715 00:23:17.245344 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.250375 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.250509 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/L2Norm[L2Norm]/2289_swim_transpose_0, op type:nndct_permute, output shape: [1, 38, 38, 512] I20230715 00:23:17.255223 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.255311 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.255378 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.255997 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_permute_C0S1NMaVgLGwBKit, with op num: 4 I20230715 00:23:17.256064 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... W20230715 00:23:17.260844 25772 PartitionPass.cpp:3741] [UNILOG][WARNING] xir::Op{name = SSD__SSD_L2Norm_L2Norm__2289_swim_transpose_0, type = transpose} has been assigned to CPU. I20230715 00:23:17.261134 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 2, DPU subgraph number 0 I20230715 00:23:17.261204 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2944, op type:nndct_reshape, output shape: [1, 16] I20230715 00:23:17.265520 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.265622 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.265686 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.265841 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_hbLuBKWYAj9Mp2zH, with op num: 7 I20230715 00:23:17.265893 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.271673 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.271802 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2961, op type:nndct_reshape, output shape: [1, 8664] I20230715 00:23:17.276579 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.276667 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.276695 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.276921 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_ruL5BkgMcQxSvWT1, with op num: 7 I20230715 00:23:17.276974 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.282996 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.283107 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2916, op type:nndct_reshape, output shape: [1, 8664] I20230715 00:23:17.287793 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.287885 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.287928 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.288166 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_CG9UxtkeBZTg5PFH, with op num: 7 I20230715 00:23:17.288225 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.292711 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.292790 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/L2Norm[L2Norm]/2278_swim_transpose_1, op type:nndct_reshape, output shape: [1, 38, 38, 1] I20230715 00:23:17.297644 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.297721 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.297777 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.298096 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_frFyNXVenWOxBA9j, with op num: 9 I20230715 00:23:17.298175 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.304850 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.304966 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2937, op type:nndct_reshape, output shape: [1, 144] I20230715 00:23:17.309127 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.309204 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.309253 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.309393 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_vmLpAPVBr1at98W5, with op num: 7 I20230715 00:23:17.309446 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.314692 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.314795 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/L2Norm[L2Norm]/2288, op type:nndct_reshape, output shape: [1, 512, 1, 1] [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2930, op type:nndct_reshape, output shape: [1, 600] I20230715 00:23:17.322743 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.322834 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.322880 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.323024 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_VrwI2GBP7HtOgEDU, with op num: 7 I20230715 00:23:17.323065 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.327647 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.327821 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2982, op type:nndct_reshape, output shape: [1, 144] I20230715 00:23:17.331908 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.331995 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.332013 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.332159 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_LYXhCHURBpldr2ki, with op num: 7 I20230715 00:23:17.332263 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.337536 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.337654 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2975, op type:nndct_reshape, output shape: [1, 600] I20230715 00:23:17.341785 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.341850 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.341886 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.342032 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_dp6BcgOyftzUZml1, with op num: 7 I20230715 00:23:17.342072 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.346367 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.346478 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2909, op type:nndct_reshape, output shape: [1, 23104] I20230715 00:23:17.350674 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.350782 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.350884 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.351091 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_jiutLvOa0FEyHC82, with op num: 7 I20230715 00:23:17.351214 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.355984 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.356070 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2968, op type:nndct_reshape, output shape: [1, 2400] I20230715 00:23:17.359956 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.360038 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.360087 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.360249 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_es6o7XMGzcLjU3O8, with op num: 7 I20230715 00:23:17.360320 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.365896 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.366040 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2954, op type:nndct_reshape, output shape: [1, 23104] I20230715 00:23:17.371043 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.371119 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.371136 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.371368 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_soOGZapKgzkfMh9C, with op num: 7 I20230715 00:23:17.371413 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.375718 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.375878 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for reshape_fix_1: node name:SSD::SSD/2989, op type:nndct_reshape, output shape: [1, 16] I20230715 00:23:17.379504 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.379591 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.379642 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.379941 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_reshape_pmxfUP0e5jar1QqJ, with op num: 7 I20230715 00:23:17.380007 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.385710 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.385856 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for pool_fix_5: node name:SSD::SSD/MaxPool2d[vgg]/ModuleList[4]/input.9, op type:nndct_maxpool, output shape: [1, 150, 150, 64] I20230715 00:23:17.405838 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.405925 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.405954 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.406073 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_maxpool_s6oOpDK75C4qZfmJ, with op num: 4 I20230715 00:23:17.406114 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.411821 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.411935 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for pool_fix_5: node name:SSD::SSD/MaxPool2d[vgg]/ModuleList[30]/input.53, op type:nndct_maxpool, output shape: [1, 19, 19, 512] I20230715 00:23:17.415522 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.415606 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.415656 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.415788 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_maxpool_cJjx1IYHOoeTWFSi, with op num: 4 I20230715 00:23:17.415841 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.423285 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.423377 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for pool_fix_5: node name:SSD::SSD/MaxPool2d[vgg]/ModuleList[9]/input.17, op type:nndct_maxpool, output shape: [1, 75, 75, 128] I20230715 00:23:17.427911 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.427985 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.428001 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.428125 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_maxpool_AMn0CWy8T3oGY9H1, with op num: 4 I20230715 00:23:17.428186 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.435724 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.435833 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for pool_fix_5: node name:SSD::SSD/MaxPool2d[vgg]/ModuleList[16]/input.29, op type:nndct_maxpool, output shape: [1, 38, 38, 256] I20230715 00:23:17.439888 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.439985 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.440050 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.440235 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_maxpool_Uzc6x2oebLFrp8A3, with op num: 4 I20230715 00:23:17.440300 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.446369 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.446451 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for pool_fix_5: node name:SSD::SSD/MaxPool2d[vgg]/ModuleList[23]/input.41, op type:nndct_maxpool, output shape: [1, 19, 19, 512] I20230715 00:23:17.450556 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.450786 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.450860 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.451157 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_maxpool_DvY2hQLM1aKwV7Nq, with op num: 4 I20230715 00:23:17.451349 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.457505 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.457630 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for concat_fix_13: node name:SSD::SSD/2992, op type:nndct_concat, output shape: [1, 34928] I20230715 00:23:17.490767 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.490856 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.490873 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.490976 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_concat_DT410tvZ6hQqU2RE, with op num: 14 I20230715 00:23:17.491044 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.505836 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 8, DPU subgraph number 1 I20230715 00:23:17.505940 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for concat_fix_13: node name:SSD::SSD/2947, op type:nndct_concat, output shape: [1, 34928] I20230715 00:23:17.512902 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.512974 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.512989 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.513110 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_concat_Azn6qxLP82G7YdcI, with op num: 14 I20230715 00:23:17.513178 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.528402 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 8, DPU subgraph number 1 I20230715 00:23:17.528503 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[4]/2813, op type:nndct_conv2d, output shape: [1, 3, 3, 16] I20230715 00:23:17.542793 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.542893 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.542910 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.543035 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_VB4RnNIYySgDsi3J, with op num: 8 I20230715 00:23:17.543076 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.555325 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.555508 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[3]/2759, op type:nndct_conv2d, output shape: [1, 5, 5, 24] I20230715 00:23:17.560678 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.560750 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.560765 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.560859 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_jaTMUo7XsnV6RZvf, with op num: 8 I20230715 00:23:17.560928 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.573191 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.573292 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[1]/2678, op type:nndct_conv2d, output shape: [1, 19, 19, 24] I20230715 00:23:17.578369 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.578470 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.578486 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.578577 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_f5Q2grLvN3iJ9HVn, with op num: 8 I20230715 00:23:17.578616 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.602905 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.603070 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[0]/2624, op type:nndct_conv2d, output shape: [1, 38, 38, 16] I20230715 00:23:17.608078 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.608175 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.608191 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.608294 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_DPmuo2gXt13v5sEh, with op num: 8 I20230715 00:23:17.608361 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.621366 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.621491 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[1]/2651, op type:nndct_conv2d, output shape: [1, 19, 19, 24] I20230715 00:23:17.626747 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.626847 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.626863 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.627043 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_ZNS68qyH7bp5RozI, with op num: 8 I20230715 00:23:17.627086 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.651890 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.651993 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[4]/2840, op type:nndct_conv2d, output shape: [1, 3, 3, 16] I20230715 00:23:17.657405 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.657483 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.657500 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.657598 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_giKbdjhVAFScXp9x, with op num: 8 I20230715 00:23:17.657660 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.668725 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.668835 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[2]/2705, op type:nndct_conv2d, output shape: [1, 10, 10, 24] I20230715 00:23:17.674247 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.674316 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.674332 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.674474 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_bXPkio5U6hO178Ay, with op num: 8 I20230715 00:23:17.674515 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.692263 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.692399 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[0]/2597, op type:nndct_conv2d, output shape: [1, 38, 38, 16] I20230715 00:23:17.697995 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.698091 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.698115 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.698272 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_BcAEDMzh7kb8yfue, with op num: 8 I20230715 00:23:17.698323 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.712138 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.712232 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[3]/2786, op type:nndct_conv2d, output shape: [1, 5, 5, 24] I20230715 00:23:17.717177 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.717304 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.717372 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.717496 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_N9yklqOpYoBxZ6XE, with op num: 8 I20230715 00:23:17.717556 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.729678 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.729815 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[2]/2732, op type:nndct_conv2d, output shape: [1, 10, 10, 24] I20230715 00:23:17.735380 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.735504 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.735540 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.735646 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_0qiHc9oavSj63LCg, with op num: 8 I20230715 00:23:17.735688 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.752334 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.752476 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[conf]/ModuleList[5]/2894, op type:nndct_conv2d, output shape: [1, 1, 1, 16] I20230715 00:23:17.756429 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.756629 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.756647 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.756739 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_lWSON5kIwVaEBUgf, with op num: 8 I20230715 00:23:17.756793 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.769004 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.769110 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_20: node name:SSD::SSD/Conv2d[loc]/ModuleList[5]/2867, op type:nndct_conv2d, output shape: [1, 1, 1, 16] I20230715 00:23:17.774561 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.774657 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.774742 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.774859 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_conv2d_NJR2Cf1q08bEvzHG, with op num: 8 I20230715 00:23:17.774897 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.787113 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.787212 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for convlike_fix_21: node name:SSD::SSD/L2Norm[L2Norm]/input.77, op type:nndct_elemwise_mul, output shape: [1, 38, 38, 512] I20230715 00:23:17.798164 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.798260 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.798318 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.798491 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_elemwise_mul_jZDeutcz286sF10W, with op num: 6 I20230715 00:23:17.798547 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.805948 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 4, DPU subgraph number 1 I20230715 00:23:17.806051 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. [VAIQ_NOTE]: Find subgraph for eltwise_fix_24: node name:SSD::SSD/L2Norm[L2Norm]/3184, op type:nndct_elemwise_add, output shape: [1, 38, 38, 1] I20230715 00:23:17.825408 25772 compile_pass_manager.cpp:287] [UNILOG][INFO] Compile mode: dpu I20230715 00:23:17.825500 25772 compile_pass_manager.cpp:288] [UNILOG][INFO] Debug mode: null I20230715 00:23:17.825577 25772 compile_pass_manager.cpp:292] [UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B1024 I20230715 00:23:17.825801 25772 compile_pass_manager.cpp:357] [UNILOG][INFO] Graph name: nndct_elemwise_add_LG2QphbdKcfk57NR, with op num: 6 I20230715 00:23:17.825871 25772 compile_pass_manager.cpp:370] [UNILOG][INFO] Begin to compile... I20230715 00:23:17.831537 25772 compile_pass_manager.cpp:381] [UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1 I20230715 00:23:17.831621 25772 compile_pass_manager.cpp:386] [UNILOG][INFO] Compile done. Traceback (most recent call last): File "ssd_quant.py", line 157, in file_path=file_path) File "ssd_quant.py", line 111, in quantization inspector.inspect(quant_model, (input,), device=device) File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/pytorch_nndct/apis.py", line 196, in inspect self._inspector_impl.inspect(module, input_args, device, output_dir, verbose_level) File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/pytorch_nndct/hardware_v3/inspector.py", line 53, in inspect self._device_allocator.process(dev_graph) File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/nndct_shared/inspector/device_allocator.py", line 36, in process self._post_process(graph) File "/opt/vitis_ai/conda/envs/vitis-ai-pytorch/lib/python3.7/site-packages/nndct_shared/inspector/device_allocator.py", line 134, in _post_process pn = graph.parents(node)[0] IndexError: list index out of range ```
takeshiho0531 commented 1 year ago

Here's the file I ran in quantizing. I did transfer learning of SSD(4 class) and then tried quantizing. In the file below, I temporarily omitted the process of checking the accuracy of quantization.


from ssd.ssd_model import SSD
import os
import re
import sys
import argparse
import time
import pdb
import random
import pytorch_nndct
from pytorch_nndct.apis import torch_quantizer
import torch
from pytorch_nndct.apis import Inspector

from tqdm import tqdm

device = torch.device("cuda" if torch.cuda.is_available() else "cpu")

parser = argparse.ArgumentParser()

parser.add_argument(
    '--model_dir',
    default="/workspace/src/vai_quantizer/vai_q_pytorch/example/ssd/trained/",
    help='Trained model file path. Download pretrained model from the following url and put it in model_dir specified path: https://download.pytorch.org/models/resnet18-5c106cde.pth'
)
parser.add_argument(
    '--config_file',
    default=None,
    help='quantization configuration file')
parser.add_argument(
    '--subset_len',
    default=None,
    type=int,
    help='subset_len to evaluate model, using the whole validation dataset if it is not set')
parser.add_argument(
    '--batch_size',
    default=32,
    type=int,
    help='input data batch size to evaluate model')
parser.add_argument('--quant_mode', 
    default='calib', 
    choices=['float', 'calib', 'test'], 
    help='quantization mode. 0: no quantization, evaluate float model, calib: quantize, test: evaluate quantized model')
parser.add_argument('--deploy', 
    dest='deploy',
    action='store_true',
    help='export xmodel for deployment')
parser.add_argument('--inspect', 
    dest='inspect',
    action='store_true',
    help='inspect model')

parser.add_argument('--target', 
    default='DPUCZDX8G_ISA1_B1024',
    dest='target',
    nargs="?",
    const="",
    help='specify target device')

args, _ = parser.parse_known_args()

def quantization(title='optimize',
                 model_name='',   # TODO
                 file_path=''): 
  quant_mode = args.quant_mode
  deploy = args.deploy
  batch_size = args.batch_size
  subset_len = args.subset_len
  inspect = args.inspect
  config_file = args.config_file
  target = args.target
  if quant_mode != 'test' and deploy:
    deploy = False
    print(r'Warning: Exporting xmodel needs to be done in quantization test mode, turn off it in this running!')
  if deploy and (batch_size != 1 or subset_len != 1):
    print(r'Warning: Exporting xmodel needs batch size to be 1 and only 1 iteration of inference, change them automatically!')
    batch_size = 1
    subset_len = 1

  ssd_cfg = {
    'num_classes': 4,  # class number including background
    'input_size': 300, 
    'bbox_aspect_num': [4, 6, 6, 6, 4, 4],  # type of aspect ratio of output default box
    'feature_maps': [38, 19, 10, 5, 3, 1], 
    'steps': [8, 16, 32, 64, 100, 300],  # decide the size of default box
    'min_sizes': [30, 60, 111, 162, 213, 264],  # decide the size of default box
    'max_sizes': [60, 111, 162, 213, 264, 315],  # decide the size of default box
    'aspect_ratios': [[2], [2, 3], [2, 3], [2, 3], [2], [2]],
  }

  model = SSD(phase="train", cfg=ssd_cfg)
  #model.cpu()
  #model.load_state_dict(torch.load(file_path))
  model_weight=torch.load(file_path, map_location={'cuda:0':'cpu'})
  model.load_state_dict(model_weight)

  input = torch.randn([batch_size, 3, 300, 300])
  if quant_mode == 'float':
    quant_model = model
    if inspect:
      if not target:
          raise RuntimeError("A target should be specified for inspector.")

      # create inspector
      inspector = Inspector(target)  # by name
      # start to inspect
      inspector.inspect(quant_model, (input,), device=device)
      sys.exit()

  else:
    ####################################################################################
    # This function call will create a quantizer object and setup it. 
    # Eager mode model code will be converted to graph model. 
    # Quantization is not done here if it needs calibration.
    quantizer = torch_quantizer(
        quant_mode, model, (input), device=device, quant_config_file=config_file, target=target)

    # Get the converted model to be quantized.
    quant_model = quantizer.quant_model
    #####################################################################################

  # handle quantization result
  if quant_mode == 'calib':
    # Exporting intermediate files will be used when quant_mode is 'test'. This is must.
    quantizer.export_quant_config()
  if deploy:
    quantizer.export_torch_script()
    quantizer.export_onnx_model()
    quantizer.export_xmodel()

if __name__ == '__main__':

  model_name = 'ssd300'
  file_path = os.path.join(args.model_dir, model_name + '.pth')

  feature_test = ' float model evaluation'
  if args.quant_mode != 'float':
    feature_test = ' quantization'
    # force to merge BN with CONV for better quantization accuracy
    args.optimize = 1
    feature_test += ' with optimization'
  else:
    feature_test = ' float model evaluation'
  title = model_name + feature_test

  print("-------- Start {} test ".format(model_name))

  # calibration or evaluation
  quantization(
      title=title,
      model_name=model_name,
      file_path=file_path)

  print("-------- End of {} test ".format(model_name))
takeshiho0531 commented 1 year ago

And here's quantize_result/SSD.py, made as 'Quantizable module' while executing python ssd_quant.py --quant_mode float --inspect --batch_size 1 --target DPUCZDX8G_ISA1_B1024. This was the only file made under quantize_result directory.

# GENETARED BY NNDCT, DO NOT EDIT!

import torch
from torch import tensor
import pytorch_nndct as py_nndct

class SSD(py_nndct.nn.NndctQuantModel):
    def __init__(self):
        super(SSD, self).__init__()
        self.module_0 = py_nndct.nn.Module('nndct_const') #SSD::3183
        self.module_1 = py_nndct.nn.Input() #SSD::input_0
        self.module_2 = py_nndct.nn.Conv2d(in_channels=3, out_channels=64, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[0]/input.3
        self.module_3 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[1]/input.5
        self.module_4 = py_nndct.nn.Conv2d(in_channels=64, out_channels=64, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[2]/input.7
        self.module_5 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[3]/2068
        self.module_6 = py_nndct.nn.MaxPool2d(kernel_size=[2, 2], stride=[2, 2], padding=[0, 0], dilation=[1, 1], ceil_mode=False) #SSD::SSD/MaxPool2d[vgg]/ModuleList[4]/input.9
        self.module_7 = py_nndct.nn.Conv2d(in_channels=64, out_channels=128, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[5]/input.11
        self.module_8 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[6]/input.13
        self.module_9 = py_nndct.nn.Conv2d(in_channels=128, out_channels=128, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[7]/input.15
        self.module_10 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[8]/2122
        self.module_11 = py_nndct.nn.MaxPool2d(kernel_size=[2, 2], stride=[2, 2], padding=[0, 0], dilation=[1, 1], ceil_mode=False) #SSD::SSD/MaxPool2d[vgg]/ModuleList[9]/input.17
        self.module_12 = py_nndct.nn.Conv2d(in_channels=128, out_channels=256, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[10]/input.19
        self.module_13 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[11]/input.21
        self.module_14 = py_nndct.nn.Conv2d(in_channels=256, out_channels=256, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[12]/input.23
        self.module_15 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[13]/input.25
        self.module_16 = py_nndct.nn.Conv2d(in_channels=256, out_channels=256, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[14]/input.27
        self.module_17 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[15]/2196
        self.module_18 = py_nndct.nn.MaxPool2d(kernel_size=[2, 2], stride=[2, 2], padding=[0, 0], dilation=[1, 1], ceil_mode=True) #SSD::SSD/MaxPool2d[vgg]/ModuleList[16]/input.29
        self.module_19 = py_nndct.nn.Conv2d(in_channels=256, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[17]/input.31
        self.module_20 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[18]/input.33
        self.module_21 = py_nndct.nn.Conv2d(in_channels=512, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[19]/input.35
        self.module_22 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[20]/input.37
        self.module_23 = py_nndct.nn.Conv2d(in_channels=512, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[21]/input.39
        self.module_24 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[22]/2270
        self.module_25 = py_nndct.nn.Module('aten::pow') #SSD::SSD/L2Norm[L2Norm]/2272
        self.module_26 = py_nndct.nn.Module('nndct_sum') #SSD::SSD/L2Norm[L2Norm]/2277
        self.module_27 = py_nndct.nn.Module('aten::sqrt') #SSD::SSD/L2Norm[L2Norm]/2278
        self.module_28 = py_nndct.nn.Add() #SSD::SSD/L2Norm[L2Norm]/3184
        self.module_29 = py_nndct.nn.Module('nndct_elemwise_div') #SSD::SSD/L2Norm[L2Norm]/2282
        self.module_30 = py_nndct.nn.Module('nndct_unsqueeze') #SSD::SSD/L2Norm[L2Norm]/2284
        self.module_31 = py_nndct.nn.Module('nndct_unsqueeze') #SSD::SSD/L2Norm[L2Norm]/2286
        self.module_32 = py_nndct.nn.Module('nndct_unsqueeze') #SSD::SSD/L2Norm[L2Norm]/2288
        self.module_33 = py_nndct.nn.expand_as() #SSD::SSD/L2Norm[L2Norm]/2289
        self.module_34 = py_nndct.nn.Module('nndct_elemwise_mul') #SSD::SSD/L2Norm[L2Norm]/input.77
        self.module_35 = py_nndct.nn.MaxPool2d(kernel_size=[2, 2], stride=[2, 2], padding=[0, 0], dilation=[1, 1], ceil_mode=False) #SSD::SSD/MaxPool2d[vgg]/ModuleList[23]/input.41
        self.module_36 = py_nndct.nn.Conv2d(in_channels=512, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[24]/input.43
        self.module_37 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[25]/input.45
        self.module_38 = py_nndct.nn.Conv2d(in_channels=512, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[26]/input.47
        self.module_39 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[27]/input.49
        self.module_40 = py_nndct.nn.Conv2d(in_channels=512, out_channels=512, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[28]/input.51
        self.module_41 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[29]/2364
        self.module_42 = py_nndct.nn.MaxPool2d(kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], ceil_mode=False) #SSD::SSD/MaxPool2d[vgg]/ModuleList[30]/input.53
        self.module_43 = py_nndct.nn.Conv2d(in_channels=512, out_channels=1024, kernel_size=[3, 3], stride=[1, 1], padding=[6, 6], dilation=[6, 6], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[31]/input.55
        self.module_44 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[32]/input.57
        self.module_45 = py_nndct.nn.Conv2d(in_channels=1024, out_channels=1024, kernel_size=[1, 1], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[vgg]/ModuleList[33]/input.59
        self.module_46 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/ReLU[vgg]/ModuleList[34]/input.61
        self.module_47 = py_nndct.nn.Conv2d(in_channels=1024, out_channels=256, kernel_size=[1, 1], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[0]/2437
        self.module_48 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.63
        self.module_49 = py_nndct.nn.Conv2d(in_channels=256, out_channels=512, kernel_size=[3, 3], stride=[2, 2], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[1]/2457
        self.module_50 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.65
        self.module_51 = py_nndct.nn.Conv2d(in_channels=512, out_channels=128, kernel_size=[1, 1], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[2]/2477
        self.module_52 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.67
        self.module_53 = py_nndct.nn.Conv2d(in_channels=128, out_channels=256, kernel_size=[3, 3], stride=[2, 2], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[3]/2497
        self.module_54 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.69
        self.module_55 = py_nndct.nn.Conv2d(in_channels=256, out_channels=128, kernel_size=[1, 1], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[4]/2517
        self.module_56 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.71
        self.module_57 = py_nndct.nn.Conv2d(in_channels=128, out_channels=256, kernel_size=[3, 3], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[5]/2537
        self.module_58 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.73
        self.module_59 = py_nndct.nn.Conv2d(in_channels=256, out_channels=128, kernel_size=[1, 1], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[6]/2557
        self.module_60 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input.75
        self.module_61 = py_nndct.nn.Conv2d(in_channels=128, out_channels=256, kernel_size=[3, 3], stride=[1, 1], padding=[0, 0], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[extras]/ModuleList[7]/2577
        self.module_62 = py_nndct.nn.ReLU(inplace=True) #SSD::SSD/input
        self.module_63 = py_nndct.nn.Conv2d(in_channels=512, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[0]/2597
        self.module_64 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2603
        self.module_65 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2605
        self.module_66 = py_nndct.nn.Conv2d(in_channels=512, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[0]/2624
        self.module_67 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2630
        self.module_68 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2632
        self.module_69 = py_nndct.nn.Conv2d(in_channels=1024, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[1]/2651
        self.module_70 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2657
        self.module_71 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2659
        self.module_72 = py_nndct.nn.Conv2d(in_channels=1024, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[1]/2678
        self.module_73 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2684
        self.module_74 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2686
        self.module_75 = py_nndct.nn.Conv2d(in_channels=512, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[2]/2705
        self.module_76 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2711
        self.module_77 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2713
        self.module_78 = py_nndct.nn.Conv2d(in_channels=512, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[2]/2732
        self.module_79 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2738
        self.module_80 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2740
        self.module_81 = py_nndct.nn.Conv2d(in_channels=256, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[3]/2759
        self.module_82 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2765
        self.module_83 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2767
        self.module_84 = py_nndct.nn.Conv2d(in_channels=256, out_channels=24, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[3]/2786
        self.module_85 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2792
        self.module_86 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2794
        self.module_87 = py_nndct.nn.Conv2d(in_channels=256, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[4]/2813
        self.module_88 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2819
        self.module_89 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2821
        self.module_90 = py_nndct.nn.Conv2d(in_channels=256, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[4]/2840
        self.module_91 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2846
        self.module_92 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2848
        self.module_93 = py_nndct.nn.Conv2d(in_channels=256, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[loc]/ModuleList[5]/2867
        self.module_94 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2873
        self.module_95 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2875
        self.module_96 = py_nndct.nn.Conv2d(in_channels=256, out_channels=16, kernel_size=[3, 3], stride=[1, 1], padding=[1, 1], dilation=[1, 1], groups=1, bias=True) #SSD::SSD/Conv2d[conf]/ModuleList[5]/2894
        self.module_97 = py_nndct.nn.Module('nndct_permute') #SSD::SSD/2900
        self.module_98 = py_nndct.nn.Module('nndct_contiguous') #SSD::SSD/2902
        self.module_99 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2904
        self.module_100 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2909
        self.module_101 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2911
        self.module_102 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2916
        self.module_103 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2918
        self.module_104 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2923
        self.module_105 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2925
        self.module_106 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2930
        self.module_107 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2932
        self.module_108 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2937
        self.module_109 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2939
        self.module_110 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2944
        self.module_111 = py_nndct.nn.Cat() #SSD::SSD/2947
        self.module_112 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2949
        self.module_113 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2954
        self.module_114 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2956
        self.module_115 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2961
        self.module_116 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2963
        self.module_117 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2968
        self.module_118 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2970
        self.module_119 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2975
        self.module_120 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2977
        self.module_121 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2982
        self.module_122 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2984
        self.module_123 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/2989
        self.module_124 = py_nndct.nn.Cat() #SSD::SSD/2992
        self.module_125 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/2994
        self.module_126 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/3000
        self.module_127 = py_nndct.nn.Module('nndct_shape') #SSD::SSD/3002
        self.module_128 = py_nndct.nn.Module('nndct_reshape') #SSD::SSD/3008
        self.L2Norm_weight = torch.nn.parameter.Parameter(torch.Tensor(512,))

    @py_nndct.nn.forward_processor
    def forward(self, *args):
        output_module_0 = self.module_0(data=1.000000013351432e-10, dtype=torch.float, device='cpu')
        output_module_1 = self.module_1(input=args[0])
        output_module_1 = self.module_2(output_module_1)
        output_module_1 = self.module_3(output_module_1)
        output_module_1 = self.module_4(output_module_1)
        output_module_1 = self.module_5(output_module_1)
        output_module_1 = self.module_6(output_module_1)
        output_module_1 = self.module_7(output_module_1)
        output_module_1 = self.module_8(output_module_1)
        output_module_1 = self.module_9(output_module_1)
        output_module_1 = self.module_10(output_module_1)
        output_module_1 = self.module_11(output_module_1)
        output_module_1 = self.module_12(output_module_1)
        output_module_1 = self.module_13(output_module_1)
        output_module_1 = self.module_14(output_module_1)
        output_module_1 = self.module_15(output_module_1)
        output_module_1 = self.module_16(output_module_1)
        output_module_1 = self.module_17(output_module_1)
        output_module_1 = self.module_18(output_module_1)
        output_module_1 = self.module_19(output_module_1)
        output_module_1 = self.module_20(output_module_1)
        output_module_1 = self.module_21(output_module_1)
        output_module_1 = self.module_22(output_module_1)
        output_module_1 = self.module_23(output_module_1)
        output_module_1 = self.module_24(output_module_1)
        output_module_25 = self.module_25({'self': output_module_1,'exponent': 2})
        output_module_25 = self.module_26(input=output_module_25, dim=1, keepdim=True)
        output_module_25 = self.module_27({'self': output_module_25})
        output_module_25 = self.module_28(input=output_module_25, other=output_module_0, alpha=1)
        output_module_29 = self.module_29(input=output_module_1, other=output_module_25)
        output_module_30 = self.module_30(input=self.L2Norm_weight, dim=0)
        output_module_31 = self.module_31(input=output_module_30, dim=2)
        output_module_32 = self.module_32(input=output_module_31, dim=3)
        output_module_32 = self.module_33(input=output_module_32, other=output_module_29)
        output_module_32 = self.module_34(input=output_module_32, other=output_module_29)
        output_module_35 = self.module_35(output_module_1)
        output_module_35 = self.module_36(output_module_35)
        output_module_35 = self.module_37(output_module_35)
        output_module_35 = self.module_38(output_module_35)
        output_module_35 = self.module_39(output_module_35)
        output_module_35 = self.module_40(output_module_35)
        output_module_35 = self.module_41(output_module_35)
        output_module_35 = self.module_42(output_module_35)
        output_module_35 = self.module_43(output_module_35)
        output_module_35 = self.module_44(output_module_35)
        output_module_35 = self.module_45(output_module_35)
        output_module_35 = self.module_46(output_module_35)
        output_module_47 = self.module_47(output_module_35)
        output_module_47 = self.module_48(output_module_47)
        output_module_47 = self.module_49(output_module_47)
        output_module_47 = self.module_50(output_module_47)
        output_module_51 = self.module_51(output_module_47)
        output_module_51 = self.module_52(output_module_51)
        output_module_51 = self.module_53(output_module_51)
        output_module_51 = self.module_54(output_module_51)
        output_module_55 = self.module_55(output_module_51)
        output_module_55 = self.module_56(output_module_55)
        output_module_55 = self.module_57(output_module_55)
        output_module_55 = self.module_58(output_module_55)
        output_module_59 = self.module_59(output_module_55)
        output_module_59 = self.module_60(output_module_59)
        output_module_59 = self.module_61(output_module_59)
        output_module_59 = self.module_62(output_module_59)
        output_module_63 = self.module_63(output_module_32)
        output_module_63 = self.module_64(dims=[0,2,3,1], input=output_module_63)
        output_module_63 = self.module_65(output_module_63)
        output_module_66 = self.module_66(output_module_32)
        output_module_66 = self.module_67(dims=[0,2,3,1], input=output_module_66)
        output_module_66 = self.module_68(output_module_66)
        output_module_69 = self.module_69(output_module_35)
        output_module_69 = self.module_70(dims=[0,2,3,1], input=output_module_69)
        output_module_69 = self.module_71(output_module_69)
        output_module_72 = self.module_72(output_module_35)
        output_module_72 = self.module_73(dims=[0,2,3,1], input=output_module_72)
        output_module_72 = self.module_74(output_module_72)
        output_module_75 = self.module_75(output_module_47)
        output_module_75 = self.module_76(dims=[0,2,3,1], input=output_module_75)
        output_module_75 = self.module_77(output_module_75)
        output_module_78 = self.module_78(output_module_47)
        output_module_78 = self.module_79(dims=[0,2,3,1], input=output_module_78)
        output_module_78 = self.module_80(output_module_78)
        output_module_81 = self.module_81(output_module_51)
        output_module_81 = self.module_82(dims=[0,2,3,1], input=output_module_81)
        output_module_81 = self.module_83(output_module_81)
        output_module_84 = self.module_84(output_module_51)
        output_module_84 = self.module_85(dims=[0,2,3,1], input=output_module_84)
        output_module_84 = self.module_86(output_module_84)
        output_module_87 = self.module_87(output_module_55)
        output_module_87 = self.module_88(dims=[0,2,3,1], input=output_module_87)
        output_module_87 = self.module_89(output_module_87)
        output_module_90 = self.module_90(output_module_55)
        output_module_90 = self.module_91(dims=[0,2,3,1], input=output_module_90)
        output_module_90 = self.module_92(output_module_90)
        output_module_93 = self.module_93(output_module_59)
        output_module_93 = self.module_94(dims=[0,2,3,1], input=output_module_93)
        output_module_93 = self.module_95(output_module_93)
        output_module_96 = self.module_96(output_module_59)
        output_module_96 = self.module_97(dims=[0,2,3,1], input=output_module_96)
        output_module_96 = self.module_98(output_module_96)
        output_module_99 = self.module_99(input=output_module_63, dim=0)
        output_module_100 = self.module_100(input=output_module_63, shape=[output_module_99,-1])
        output_module_101 = self.module_101(input=output_module_69, dim=0)
        output_module_102 = self.module_102(input=output_module_69, shape=[output_module_101,-1])
        output_module_103 = self.module_103(input=output_module_75, dim=0)
        output_module_104 = self.module_104(input=output_module_75, shape=[output_module_103,-1])
        output_module_105 = self.module_105(input=output_module_81, dim=0)
        output_module_106 = self.module_106(input=output_module_81, shape=[output_module_105,-1])
        output_module_107 = self.module_107(input=output_module_87, dim=0)
        output_module_108 = self.module_108(input=output_module_87, shape=[output_module_107,-1])
        output_module_109 = self.module_109(input=output_module_93, dim=0)
        output_module_110 = self.module_110(input=output_module_93, shape=[output_module_109,-1])
        output_module_100 = self.module_111(dim=1, tensors=[output_module_100,output_module_102,output_module_104,output_module_106,output_module_108,output_module_110])
        output_module_112 = self.module_112(input=output_module_66, dim=0)
        output_module_113 = self.module_113(input=output_module_66, shape=[output_module_112,-1])
        output_module_114 = self.module_114(input=output_module_72, dim=0)
        output_module_115 = self.module_115(input=output_module_72, shape=[output_module_114,-1])
        output_module_116 = self.module_116(input=output_module_78, dim=0)
        output_module_117 = self.module_117(input=output_module_78, shape=[output_module_116,-1])
        output_module_118 = self.module_118(input=output_module_84, dim=0)
        output_module_119 = self.module_119(input=output_module_84, shape=[output_module_118,-1])
        output_module_120 = self.module_120(input=output_module_90, dim=0)
        output_module_121 = self.module_121(input=output_module_90, shape=[output_module_120,-1])
        output_module_122 = self.module_122(input=output_module_96, dim=0)
        output_module_123 = self.module_123(input=output_module_96, shape=[output_module_122,-1])
        output_module_113 = self.module_124(dim=1, tensors=[output_module_113,output_module_115,output_module_117,output_module_119,output_module_121,output_module_123])
        output_module_125 = self.module_125(input=output_module_100, dim=0)
        output_module_126 = self.module_126(input=output_module_100, shape=[output_module_125,-1,4])
        output_module_127 = self.module_127(input=output_module_113, dim=0)
        output_module_128 = self.module_128(input=output_module_113, shape=[output_module_127,-1,4])
        return (output_module_126,output_module_128)
takeshiho0531 commented 1 year ago

I tried this to see if it might be close, but it didn't work....